基于FPGA的简易示波器、频谱仪

2017.4: * Version 9.0 (Rev. 14) * General: Clock frequency improvement for floating point FFT. No change in functionality. * General: Bugfix in C model to resolve data-dependent incorrect block exponent when modelling the Pipelined, Streaming I/O architecture with a Block Floating Point datapath. * Revision change in one or more subcores 2017.3: * Version 9.0 (Rev. 13) * General: Comment change in C model. No change to functionality * Revision change in one or more subcores 2017.2: * Version 9.0 (Rev. 12) * No changes 2017.1: * Version 9.0 (Rev. 12) * General: Bugfix for incorrect Pipelined, Streaming I/O architecture overflow output. Due to the nature of the streaming dataflow, the final value of overflow is only guaranteed on the last cycle of data output. * General: Cleaned up C model MEX compilation warnings and added option to use -DNO_WARNINGS to mute warnings regarding real-only input data. * General: Clock frequency improvement for fixed-point Pipelined, Streaming I/O architecture by utilizing write-first BRAM mode. No change in functionality. * General: Bugfix for incorrect automatic architecture selection when only point size changed on GUI prior to generation. * General: Bugfix in C model to resolve incorrect output from Windows model when using large input or phase factor widths. 2016.4: * Version 9.0 (Rev. 11) * No changes 2016.3: * Version 9.0 (Rev. 11) * General: Support for Spartan7 devices * Revision change in one or more subcores 2016.2: * Version 9.0 (Rev. 10) * No changes 2016.1: * Version 9.0 (Rev. 10) * Revision change in one or more subcores 2015.4.2: * Version 9.0 (Rev. 9) * No changes 2015.4.1: * Version 9.0 (Rev. 9) * No changes 2015.4: * Version 9.0 (Rev. 9) * Revision change in one or more subcores 2015.3: * Version 9.0 (Rev. 8) * Bugfix for incorrect output data in block floating point mode for Radix-2 architecture when resets are applied close together * C model runtime performance improvement * Reduced the number of warning messages seen during simulator elaboration * Corrected HDL assertion logic in simulation-only checker which was missing a reset clause * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances * Bugfix for incorrect input range detection for Radix-2 Lite architecture using block floating point scaling * Revision change in one or more subcores 2015.2.1: * Version 9.0 (Rev. 7) * No changes 2015.2: * Version 9.0 (Rev. 7) * No changes 2015.1: * Version 9.0 (Rev. 7) * Bugfix for occasional (data-dependent) incorrect Block Exponent output in Radix-2 Lite architecture * Addition of Beta support for future devices * Supported devices and production status are now determined automatically, to simplify support for future devices * C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support 2014.4.1: * Version 9.0 (Rev. 6) * No changes 2014.4: * Version 9.0 (Rev. 6) * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf 2014.3: * Version 9.0 (Rev. 5) * Rephrasing code in hybrid butterfly sub-modules to avoid vopt error during Questa elaboration. Functionality is unchanged. 2014.2: * Version 9.0 (Rev. 4) * No changes 2014.1: * Version 9.0 (Rev. 4) * Removed duplicate VHDL process from Radix-2 architecture which caused multiple driver synthesis errors with Vivado 2014.1 * C models for Windows are compiled using Microsoft Visual Studio 2012 * Rephrasing code in file r22_twos_comp_mux.vhd. Functionality is unchanged. * Rephrasing code in file xfft_v9_0_viv.vhd. Functionality is unchanged. * Internal device family name change, no functional changes * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done * Enable third party synthesis tools to read encrypted netlists (but not source HDL) * c_compare_carry_structure, c_compare_eq_ne, c_mux_bit_v12_0_viv and c_shift_ram_v12_0_legacy vhd files rephrased to eliminate warnings. Functionality unaffected. * Support for Virtex Ultrascale devices at Pre-Production Status 2013.4: * Version 9.0 (Rev. 3) * Change to end of simulation message in demonstration testbench. * Support for Kintex Ultrascale devices at Pre-Production Status 2013.3: * Version 9.0 (Rev. 2) * Cosmetic GUI changes to table header row, no change in functionality * Internal standardization in source file delivery, does not change behavior * Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status * Added default constraints for out of context flow * Added support for Cadence IES and Synopsys VCS simulators * Optimized support for UltraScale devices * Fixed demonstration testbench elaboration errors - see Xilinx Answer 56322. * Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler * Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008 2013.2: * Version 9.0 (Rev. 1) * Support for Series 7 devices at Production status * Beta support for future devices * Removing support for Defense Grade Low Power Artix7 * Fix for AR53087 2013.1: * Version 9.0 * Native Vivado Release * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. (c) Copyright 2000 - 2017 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. 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