ov9650及sccb（i2c）协议_ov9650Verilog配置资源-CSDN文库

ov9650

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Version 1.3, September 24, 2004 Proprietary to OmniVision Technologies 1

Advanced Information

Preliminary Datasheet

OV9650 Color CMOS SXGA (1.3 MegaPixel) CAMERACHIP

with OmniPixel

Technology

mni

ision

General Description

The OV9650 CAMERACHIP

is a low voltage CMOS

image sensors that provides the full functionality of a

single-chip SXGA (1280x1024) camera and image

processor in a small footprint package. The OV9650

provides full-frame, sub-sampled or windowed 8-bit/10-bit

images in a wide range of formats, controlled through the

Serial Camera Control Bus (SCCB) interface.

This product has an image array capable of operating at

up to 15 frames per second (fps) in SXGA resolution with

complete user control over image quality, formatting and

output data transfer. All required image processing

functions, including exposure control, gamma, white

balance, color saturation, hue control, white pixel

canceling, noise canceling, and more, are also

programmable through the SCCB interface. In addition,

OmniVision C

AMERACHIPS use proprietary sensor

technology to improve image quality by reducing or

eliminating common lighting/electrical sources of image

contamination, such as fixed pattern noise, smearing,

etc., to produce a clean, fully stable color image.

Features

• High sensitivity for low-light operation

• Low operating voltage for embedded portable

applications

• Standard SCCB interface

• Supports SXGA, VGA, QVGA, QQVGA, CIF, QCIF,

QQCIF, and windowed outputs with Raw RGB, RGB

(GRB 4:2:2), YUV (4:2:2) and YCbCr (4:2:2) formats

• VarioPixel

method for sub-sampling formats

(VGA, QVGA, QQVGA, CIF, QCIF, and QQCIF)

• Automatic image control functions including:

Automatic Exposure Control (AEC), Automatic Gain

Control (AGC), Automatic White Balance (AWB),

Automatic Band Filter (ABF), and Automatic

Black-Level Calibration (ABLC)

• Image quality controls including color saturation,

hue, gamma, sharpness (edge enhancement), lens

correction, white pixel canceling, noise canceling and

50/60 Hz luminance detection

Ordering Information

Product Package

OV09650-KL1A (Color) CSP-28

Applications

• Cellular and Picture Phones

•Toys

• PC Multimedia

• Digital Still Cameras

Key Specifications

Figure 1 OV9650 Pin Diagram

Active Array Size 1300 x 1028

Power Supply

Core 1.8VDC +

10%

Analog 2.45 to 2.8 VDC

I/O 2.5V to 3.3V

Power

Requirements

Active

50 mW (15 fps, no I/O

power)

Standby 30 µW

Temperature

Range

Operation -20°C to 70°C

Stable Image 0°C to 50°C

Output Formats (8-bit)

• YUV/YCbCr 4:2:2

• GRB 4:2:2

• Raw RGB Data

Lens Size 1/4"

Maximum

Image

Transfer Rate

SXGA 15 fps

VGA 30 fps

QVGA, QQVGA, CIF 60 fps

QCIF, QQCIF 120 fps

Sensitivity 0.9 v/Lux-sec

S/N Ratio 40 dB

Dynamic Range 62 dB

Scan Mode Progressive

Maximum Exposure Interval 1050 x t

ROW

Gamma Correction Programmable

Pixel Size 3.18 µm x 3.18 µm

Dark Current 30 mV/s at 60°C

Well Capacity 28 K e

Fixed Pattern Noise <0.03% of V

PEAK-TO-PEAK

Image Area 4.13 mm x 3.28 mm

Package Dimensions 5095 µm x 5715 µm

OV9650

AGND

SIO_D

B2B1

SIO_C

RESET

E3E2

PWDN

AVDD

HREF

VREF

NVDD

VSYNC

DOVDD

NCDVDD

F4 F5

DOGND

F3F2F1

PCLK XVCLK1

Functional Description

Version 1.3, September 24, 2004 Proprietary to OmniVision Technologies 3

mni ision

Image Sensor Array

The OV9650 sensor has an active image array of 1300

columns by 1028 rows (1,336,400 pixels). Figure 3 shows

a cross-section of the image sensor array.

Figure 3 Image Sensor Array

Timing Generator

In general, the timing generator controls the following

functions:

• Array control and frame generation (7 different

format outputs)

• Internal timing signal generation and distribution

• Frame rate timing

• Automatic Exposure Control (AEC)

• External timing outputs (VSYNC, HREF/HSYNC, and

PCLK)

Analog Signal Processor

This block performs all analog image functions including:

• Automatic Gain Control (AGC)

• Automatic White Balance (AWB)

A/D Converters

After the Analog Processing block, the bayer pattern Raw

signal is fed to two 10-bit analog-to-digital (A/D)

converters via two multiplexers, one for the G channel and

one shared by the BR channels. These A/D converters

operate at speeds up to 12 MHz and are fully synchronous

to the pixel rate (actual conversion rate is related to the

frame rate).

Glass

Microlens

Blue

Green

Red

In addition to the A/D conversion, this block also has the

following functions:

• Digital Black-Level Calibration (BLC)

• Optional U/V channel delay

• Additional A/D range controls

In general, the combination of the A/D Range Multiplier

and A/D Range Control sets the A/D range and maximum

value to allow the user to adjust the final image brightness

as a function of the individual application.

Digital Signal Processor (DSP)

This block controls the interpolation from Raw data to

RGB and some image quality control.

• Edge enhancement (a two-dimensional high pass

filter)

• Color space converter (can change Raw data to RGB

or YUV/YCbCr)

• RGB matrix to eliminate color cross talk

• Hue and saturation control

• Programmable gamma control

• Transfer 10-bit data to 8-bit

• White pixel canceling

• De-noise

Output Formatter

This block controls all output and data formatting required

prior to sending the image out.

Digital Video Port

drive current

and can be adjusted as a function of the customer’s

SCCB Interface

The Serial Camera Control Bus (SCCB) interface controls

the C

AMERACHIP operation. Refer to OmniVision

Technologies Serial Camera Control Bus (SCCB)

Specification for detailed usage of the serial control port.

4 Proprietary to OmniVision Technologies Version 1.3, September 24, 2004

OV9650 Color CMOS SXGA (1.3 MegaPixel) OmniPixel™ CAMERACHIP™

mni ision

Pin Description

NOTE:

D[9:2] for 8-bit YUV or RGB565/RGB555 (D[9] MSB, D[2] LSB)

D[9:0] for 10-bit Raw RGB data (D[9] MSB, D[0] LSB)

Table 1 Pin Description

Pin Location Name Pin Type Function/Description

A1 PWDN

Function

(default = 0)

Power Down Mode Selection - active high, internal pull-down resistor.

0: Normal mode

1: Power down mode

A2 AVDD Power Analog power supply (V

DD-A

= 2.45 to 2.8 VDC)

A3 SIO_D I/O SCCB serial interface data I/O

A4 D2 Output Output bit[2] - LSB for 8-bit YUV or RGB565/RGB555

A5 D4 Output Output bit[4]

B1 VREF V

REF

Internal voltage reference - connect to ground through 1µF capacitor

B2 NVDD V

REF

Voltage reference

B3 AGND Power Analog ground

B4 SIO_C Input SCCB serial interface clock input

B5 D3 Output Output bit[3]

C1 D0 Output Output bit[0] - LSB for 10-bit Raw RGB data only

C2 DVDD Power Power supply (V

DD-C

= 1.8 VDC + 10%) for digital core logic

C4 NC — No connection

C5 D5 Output Output bit[5]

D1 D1 Output Output bit[1] - for 10-bit RGB only

D2 VSYNC Output Vertical sync output

D4 NC — No connection

D5 NC — No connection

E1 HREF Output HREF output

E2 DOVDD Power Digital power supply (V

DD-IO

= 2.5 to 3.3 VDC) for I/O

E3 RESET

Function

(default = 0)

Clears all registers and resets them to their default values. Active high, internal

pull-down resistor.

E4 D8 Output Output bit[8]

E5 D6 Output Output bit[6]

F1 PCLK Output Pixel clock output

F2 XVCLK1 Input System clock input

F3 DOGND Power Digital ground

F4 D9 Output Output bit[9] - MSB for 10-bit Raw RGB data and 8-bit YUV or RGB565/RGB555

F5 D7 Output Output bit[7]

接1uf电容到地

通常直接接地

SCCB协议I/O

clock信号

行有效信号

数字IO电源，通常3.3V

数字逻辑电源通常选1.8V

电源通常2.5V

复位，内部接下拉电阻，高电平有效。复位所有寄存器

像素时钟信号

系统时钟输入

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