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AT32AP7001英文数据手册
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2010-02-15
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AT32AP7001英文数据手册, AT32AP7001英文数据册,英文还要什么分
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Features
• High Performance, Low Power AVR
®
32 32-Bit Microcontroller
– 210 DMIPS throughput at 150 MHz
– 16 KB instruction cache and 16 KB data caches
– Memory Management Unit enabling use of operating systems
– Single-cycle RISC instruction set including SIMD and DSP instructions
– Java Hardware Acceleration
• Pixel Co-Processor
– Pixel Co-Processor for video acceleration through color-space conversion
(YUV<->RGB), image scaling and filtering, quarter pixel motion compensation
• Multi-hierarchy bus system
– High-performance data transfers on separate buses for increased performance
• Data Memories
– 32KBytes SRAM
• External Memory Interface
– SDRAM, DataFlash
™
, SRAM, Multi Media Card (MMC), Secure Digital (SD),
– Compact Flash, Smart Media, NAND Flash
• Direct Memory Access Controller
– External Memory access without CPU intervention
• Interrupt Controller
– Individually maskable Interrupts
– Each interrupt request has a programmable priority and autovector address
• System Functions
– Power and Clock Manager
– Crystal Oscillator with Phase-Lock-Loop (PLL)
– Watchdog Timer
– Real-time Clock
• 6 Multifunction timer/counters
– Three external clock inputs, I/O pins, PWM, capture and various counting
capabilities
• 4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– 115.2 kbps IrDA Modulation and Demodulation
– Hardware and software handshaking
• 3 Synchronous Serial Protocol controllers
– Supports I2S, SPI and generic frame-based protocols
• Two-Wire Interface
– Sequential Read/Write Operations, Philips’ I2C© compatible
• Image Sensor Interface
– 12-bit Data Interface for CMOS cameras
• Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device
– On-chip Transceivers with physical interface
• 16-bit stereo audio bitstream DAC
– Sample rates up to 50 kHz
• On-Chip Debug System
– Nexus Class 3
– Full speed, non-intrusive data and program trace
– Runtime control and JTAG interface
• Package/Pins
– AT32AP7001: 208-pin QFP/ 90 GPIO pins
• Power supplies
– 1.65V to1.95V VDDCORE
– 3.0V to 3.6V VDDIO
32015G-AVR32-09/09
AVR
®
32 32-bit
Microcontroller
AT32AP7001
Preliminary
2
32015G–AVR32–09/09
AT32AP7001
1. Part Description
The AT32AP7001 is a complete System-on-chip application processor with an AVR32 RISC
processor achieving 210 DMIPS running at 150 MHz. AVR32 is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular empha-
sis on low power consumption, high code density and high application performance.
AT32AP7001 implements a Memory Management Unit (MMU) and a flexible interrupt controller
supporting modern operating systems and real-time operating systems. The processor also
includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom
applications.
AT32AP7001 incorporates SRAM memories on-chip for fast and secure access. For applica-
tions requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM
controller provides off-chip volatile memory access as well as controllers for all industry standard
off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital
(SD)-card, SmartCard, NAND Flash and Atmel DataFlash™.
The Direct Memory Access controller for all the serial peripherals enables data transfer between
memories without processor intervention. This reduces the processor overhead when transfer-
ring continuous and large data streams between modules in the MCU.
The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform a wide range of functions including frequency measure-
ment, event counting, interval measurement, pulse generation, delay timing and pulse width
modulation.
A pixel co-processor provides color space conversions for images and video, in addition to a
wide variety of hardware filter support
Synchronous Serial Controllers provide easy access to serial communication protocols, audio
standards like I2S and frame-based protocols.
The Java hardware acceleration implementation in AVR32 allows for a very high-speed Java
byte-code execution. AVR32 implements Java instructions in hardware, reusing the existing
RISC data path, which allows for a near-zero hardware overhead and cost with a very high
performance.
The Image Sensor Interface supports cameras with up to 12-bit data buses.
PS2 connectivity is provided for standard input devices like mice and keyboards.
AT32AP7001 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control.
The C-compiler is closely linked to the architecture and is able to utilize code optimization fea-
tures, both for size and speed.
3
32015G–AVR32–09/09
AT32AP7001
2. Signals Description
The following table gives details on the signal name classified by peripheral. The pinout multi-
plexing of these signals is given in the Peripheral Muxing table in the Peripherals chapter.
Table 2-1. Signal Description List
Signal Name Function Type
Active
Level Comments
Power
AVDDPLL PLL Power Supply Power 1.65 to 1.95 V
AVDDUSB USB Power Supply Power 1.65 to 1.95 V
AVDDOSC Oscillator Power Supply Power 1.65 to 1.95 V
VDDCORE Core Power Supply Power 1.65 to 1.95 V
VDDIO I/O Power Supply Power 3.0 to 3.6V
AGNDPLL PLL Ground Ground
AGNDUSB USB Ground Ground
AGNDOSC Oscillator Ground Ground
GND Ground Ground
Clocks, Oscillators, and PLL’s
XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog
XOUT0, XOUT1,
XOUT32
Crystal 0, 1, 32 Output Analog
PLL0, PLL1 PLL 0,1 Filter Pin Analog
JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
TRST_N Test Reset Input Low
Auxiliary Port - AUX
MCKO Trace Data Output Clock Output
MDO0 - MDO5 Trace Data Output Output
MSEO0 - MSEO1 Trace Frame Control Output
EVTI_N Event In Input Low
4
32015G–AVR32–09/09
AT32AP7001
EVTO_N Event Out Output Low
Power Manager - PM
GCLK0 - GCLK4 Generic Clock Pins Output
OSCEN_N Oscillator Enable Input Low
RESET_N Reset Pin Input Low
WAKE_N Wake Pin Input Low
External Interrupt Controller - EIC
EXTINT0 - EXTINT3 External Interrupt Pins Input
NMI_N Non-Maskable Interrupt Pin Input Low
AC97 Controller - AC97C
SCLK AC97 Clock Signal Input
SDI AC97 Receive Signal Output
SDO AC97 Transmit Signal Output
SYNC AC97 Frame Synchronization Signal Input
Audio Bitstream DAC - ABDAC
DATA0 - DATA1 D/A Data Out Output
DATAN0 - DATAN1 D/A Inverted Data Out Output
External Bus Interface - EBI
PX0 - PX53 I/O Controlled by EBI I/O
ADDR0 - ADDR25 Address Bus Output
CAS Column Signal Output Low
CFCE1 Compact Flash 1 Chip Enable Output Low
CFCE2 Compact Flash 2 Chip Enable Output Low
CFRNW Compact Flash Read Not Write Output
DATA0 - DATA31 Data Bus I/O
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NCS0 - NCS5 Chip Select Output Low
Table 2-1. Signal Description List
Signal Name Function Type
Active
Level Comments
5
32015G–AVR32–09/09
AT32AP7001
NRD Read Signal Output Low
NWAIT External Wait Signal Input Low
NWE0 Write Enable 0 Output Low
NWE1 Write Enable 1 Output Low
NWE3 Write Enable 3 Output Low
RAS Row Signal Output Low
SDA10 SDRAM Address 10 Line Output
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output
SDWE SDRAM Write Enable Output Low
Image Sensor Interface - ISI
DATA0 - DATA11 Image Sensor Data Input
HSYNC Horizontal Synchronization Input
PCLK Image Sensor Data Clock Input
VSYNC Vertical Synchronization Input
MultiMedia Card Interface - MCI
CLK Multimedia Card Clock Output
CMD0 - CMD1 Multimedia Card Command I/O
DATA0 - DATA7 Multimedia Card Data I/O
Parallel Input/Output - PIOA, PIOB, PIOC, PIOD, PIOE
PA0 - PA31 Parallel I/O Controller PIOA I/O
PB0 - PB30 Parallel I/O Controller PIOB I/O
PD0 - PD17 Parallel I/O Controller PIOD I/O
PE0 - PE26 Parallel I/O Controller PIOE I/O
PS2 Interface - PSIF
CLOCK0 - CLOCK1 PS2 Clock Input
DATA0 - DATA1 PS2 Data I/O
Serial Peripheral Interface - SPI0, SPI1
Table 2-1. Signal Description List
Signal Name Function Type
Active
Level Comments
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