没有合适的资源?快使用搜索试试~ 我知道了~
STL6288:超低耗视频解码芯片CVBS/S-Video转BT656
5星 · 超过95%的资源 需积分: 45 74 下载量 13 浏览量
2016-12-14
16:41:43
上传
评论 3
收藏 5.37MB PDF 举报
温馨提示
试读
40页
STL6288:超低耗视频解码芯片CVBS转BT656,S-Video转BT656
资源推荐
资源详情
资源评论
INSPIRE
STL6288
Ultralow Power NTSC/PAL Video Decoder
Data Manual
V1.0 March 2016
18218088355 Q463449374
18218088355 Q463449374
STL6288 INSPIRE
1
STL6288
Ultralow Power NTSC/PAL Video Decoder
1 Introduction
The STL6288 device is an ultralow power NTSC/PAL/ video decoder. Available in
a space saving 32pin QFN package, the STL6288 decoder converts NTSC and PAL
video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The
optimized architecture of the STL6288 decoder allows for ultralow-power
consumption. The decoder uses just one crystal for all supported standards, or any
frequency between 10 MHz and 50MHz. The STL6288 decoder can be
programmed using an I
2
C serial interface. The decoder uses a 1.8V supply for its
analog and digital supplies, and a 3.3Vor 1.8V supply for its I/O.
The STL6288 decoder converts baseband analog video into digital YCbCr 4:2:2
component video. Composite and S-video inputs are supported. The STL6288
decoder includes one 9-bit analog-to-digital converter (ADC) with 2x sampling.
Sampling is ITU-R BT.601 (27.0 MHz, generated from the 14.31818-MHz crystal
or oscillator input) and is line-locked. The output formats can be 8-bit 4:2:2 or 8-bit
ITU-R BT.656 with embedded synchronization.
2 Features
a) High-speed 30MSPS 9-bit ADC
b) Accepts NTSC (M,J,4.43), PAL (B, D, G, H, I, M, N, NC) video data
c) Two composite inputs or one S-video input
d) Brightness, contrast, saturation, hue, and sharpness control through I
2
C
e) Standard programmable video output format:
-ITU-R BT.656, 8-bit 4:2:2 with embedded syncs
-8bit 4:2:2 ITU-R BT.601 with discrete syncs
f) programmable output position and windth of HSYNC,VSYNC and FID
g) Patented Architecture for Locking to Weak, Noisy, or Unstable Signals
h) Internal phase-locked loop (PLL) for line-locked clock and sampling
i) Wide frequency Input from 10MHz to 50MHz
j) Power-on reset
k) 32pin QFN package.
l) 3.3Vor 1.8V supply for its I/O
3 Ordering Information
Part Number Package Package Option
STL688 QFN32 Reel
4 Terminal Assignments
The STL6288 video decoder bridge is packaged in a 32-terminal QFN package.
Figure 1 shows the terminal diagram for the packages. Table 1 gives a description
of the terminals.
18218088355 Q463449374
Ultralow Power NTSC/PAL Video Decoder
STL6288
Fig. 1 STL628
Terminal Diagrams ( Top View )
Tab. 1 Terminal Functions
TERMINAL
NAME NO.
I/O DESCRIPTION
Analog Section
AGND 7 I Substrate. Connect to analog ground.
AIP1A 1 I Analog input. Connect to the video analog input via
0.1µF capacitor. The maximum input range is 0-0.75
V
PP
, and may require an attenuator to reduce the
input amplitude to the desired level. If not used,
connect to AGND via a 0.1µF capacitor.
AIP1B 2 I Analog input. Connect to the video analog input via
0.1µF capacitor. The maximum input range is 0-0.75
V
PP
, and may require an attenuator to reduce the
input amplitude to the desired level. If not used,
connect to AGND via a 0.1µF capacitor.
CH_AGND 31 I Analog ground
CH_AVDD 32 I Analog supply. Connect to 1.8V analog supply.
PLL_AGND 3 I PLL groud. Connect to analog ground.
PLL_AVDD 4 I PLL supply. Connect to 1.8V analog supply.
REFM 30 I A/D reference ground. Connect to analog ground
through a 1µF capacitor. Also, it is recommended to
connect directly to REFP through a 1µF capacitor.
REFP 29 I A/D reference supply. Connect to analog ground
through a 1µF capacitor
1
Q463449374
Ultralow Power NTSC/PAL Video Decoder
STL6288
2
Digital Section
AVID 26 O Active video indicator. This signal is high during
the horizontal active time of the video output.
AVID toggling during vertical blanking intervals is
controlled by bit 2 of the active video cropping
start pixel LSB register at address 12h.
DGND 19 I Digital ground
DVDD 20 I Digital supply. Connect to 1.8V digital supply.
FID/GLCO 23 O FID: Odd/even field indicator or vertical lock
indicator. For the odd/even indicator, a 1 indicates
the odd field.
GLCO: This serial output carries color PLL
information. A slave device can decode the
information to allow chroma frequency control
from the STL6288 decoder. Data is transmitted at
the SCLK rate in Genlock mode. In RTC mode,
SCLK/4 is used.
HSYNC 25 O Horizontal synchronization
INTERQ/GPCL/VBLK 27 I/O INTREQ: Interrupt request output
GPCL/VBLK: General-purpose control logic. This
terminal has two functions:
GPCL:.General-purpose output. In this mode the
state of GPCL is directly programmed via I
2
C.
VBLK: Vertical blank output. In this mode the
GPCL terminal indicates the vertical blanking
interval of the output video. The beginning and end
times of this signal are programmable via I
2
C.
IO_DVDD 10 I Digital supply. Connect to 3.3 V or 1.8V.
PCLK/SCLK 9 O System clock at either 1× or 2× the frequency of
the pixel clock.
PDN 28 I Power Down terminal(active low). Puts the
decoder in standby mode. Preserves the value of
registers.
RESETB 8 I Active low reset. RESETB can be used only when
PDN=H. When RESETB is pulled low, it resets all
the registers and restarts the internal
microprocessor.
SCL 21 I /O I
2
C serial clock (open drain)
SDA 22 I /O I
2
C serial data (open drain)
VSYNC/PAL1 24 O VSYNC: Vertical synchronization signal
PALI: PAL line indicator or horizontal lock
indicator. For the PAL line indicator:
1 = Noninverted line
Q463449374
Ultralow Power NTSC/PAL Video Decoder
STL6288
3
0 = Inverted line
XTAL1/OSC 5 I /O
XTAL2 6 I /O
External clock reference. The user may connect
to an oscillator or to one terminal of a crystal
oscillator . The user may connect XTAL2 to the
other terminal of the crystal oscillator or not
connect XTAL2 at all. Crystal or oscillator of
any frequency
between 10 MHz and 50MHz
is
needed for ITU-R BT.601 sampling, for all
supported standards.
YOUT[6:0] 12,13,14,15,
16,17,18
I /O
Output decoded ITU-R BT.656 output/YCbCr
4:2:2 output with discrete sync
YOUT7/I
2
CSEL 11 I /O I
2
CSEL: Determines address for I
2
C (sampled
during reset). A pullup or pulldown register is
needed (>1 kW) to program the terminal to the
desired address.
1 = Address is 0xBA
0 = Address is 0xB8
YOUT7: Most-significant bit (MSB) of output
decoded ITU-R BT.656 output /YCbCr 4:2:2
output
5 Functional Description
5.1 Analog Front End
The STL6288 decoder has an analog input channel that accepts two ac-coupled
video inputs. The decoder supports a maximum input voltage range of 0.75 V;
therefore, an attenuation of one-half is needed for most input signals with a
peak-to-peak variation of 1.5 V. The maximum parallel termination before the input
to the device is 75Ω. See the application diagram in Fig.11 for the recommended
configuration. The two analog input ports can be connected as follows:
· Two selectable composite video inputs
· One S-video input
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
The programmable gain amplifier (PGA) and the automatic gain control (AGC)
circuit work together to make sure that the input signal is amplified sufficiently to
ensure the proper input range for the ADC.
The ADC has nine bits of resolution and runs at a maximum speed of 27 MHz. The
clock input for the ADC comes from the PLL.
5.2 Composite Processing Block Diagram
The composite processing block processes NTSC/PAL signals into the YCbCr color
space.
Fig.2 shows the basic architecture of this processing block.
Fig.2 shows the luminance/chrominance (Y/C) separation process in the STL6288
decoder. The composite video is multiplied by subcarrier signals in the quadrature
modulator to generate the color difference signals Cb and Cr. Cb and Cr are then
Q463449374
剩余39页未读,继续阅读
资源评论
- sosa_gu2017-08-09跟TI5150 pin-2-pin,我手里有驱动
- chivas12072019-01-08国产的5150,胜在价格优势。
wode1212008
- 粉丝: 79
- 资源: 9
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功