################################################################################
# Vivado (TM) v2015.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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黑金xlinx AX7101+ 视频图像 GTP 光纤传输例程verilog程序 (994个子文件)
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
compile.bat 224B
simulate.bat 224B
ov5640_ddr_vga.bin 3.65MB
ov5640_ddr_vga.bit 3.65MB
gt_rom_init_tx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_tx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_tx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_tx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_tx.dat 11KB
gt_rom_init_rx.dat 11KB
gt_rom_init_tx.dat 11KB
gt_rom_init_rx.dat 11KB
ov5640_ddr_vga_routed.dcp 9.17MB
ov5640_ddr_vga_placed.dcp 7.46MB
ov5640_ddr_vga_opt.dcp 5.29MB
ddr3.dcp 2.98MB
ddr3.dcp 2.98MB
ila_0.dcp 731KB
ila_0.dcp 731KB
gtp.dcp 634KB
gtp.dcp 634KB
gtp.dcp 634KB
ov5640_ddr_vga.dcp 468KB
wrfifo.dcp 295KB
wrfifo.dcp 295KB
rdfifo.dcp 295KB
rdfifo.dcp 295KB
fifo_2048_32i_8o.dcp 177KB
fifo_2048_32i_8o.dcp 177KB
fifo_4096_16i_32o.dcp 165KB
fifo_4096_16i_32o.dcp 165KB
pll.dcp 12KB
pll.dcp 12KB
compile.do 10KB
compile.do 10KB
gtp_TB_compile.do 2KB
compile.do 986B
compile.do 980B
compile.do 956B
compile.do 950B
compile.do 901B
compile.do 895B
compile.do 541B
compile.do 541B
gtp_TB_simulate.do 540B
compile.do 533B
compile.do 533B
compile.do 527B
compile.do 525B
compile.do 519B
compile.do 517B
gtp_TB_wave.do 383B
compile.do 370B
compile.do 364B
simulate.do 296B
simulate.do 295B
simulate.do 294B
simulate.do 293B
simulate.do 292B
simulate.do 292B
simulate.do 292B
simulate.do 273B
simulate.do 273B
simulate.do 211B
simulate.do 209B
simulate.do 189B
simulate.do 189B
simulate.do 187B
simulate.do 185B
simulate.do 183B
simulate.do 183B
simulate.do 183B
elaborate.do 168B
elaborate.do 167B
elaborate.do 166B
elaborate.do 165B
elaborate.do 164B
elaborate.do 164B
elaborate.do 164B
simulate.do 158B
simulate.do 158B
simulate.do 158B
simulate.do 158B
simulate.do 158B
simulate.do 158B
simulate.do 158B
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