UG472 (v1.14) July 30, 2018 www.xilinx.com 7 Series FPGAs Clocking Resources User Guide
Revision History
The following table shows the revision history for this document.
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Date Version Revision
03/01/2011 1.0 Initial Xilinx release.
03/28/2011 1.1 Updated disclaimer and copyright on page 2. Updated Clocking Architecture Overview
and Figure 2-2. Revised the discussion in Clock-Capable Inputs including adding
Table 1-1 and Figure 2-1. Revised some of the Global Clock Buffers descriptions. Revised
the description under Figure 2-17. Updated the I/O Clock Buffer—BUFIO section.
Updated Figure 2-20. Updated the Regional Clock Buffer—BUFR section. Updated the
description in Table 2-8. Revised Figure 2-23. Added the BUFMRCE to the BUFMR
Primitive section including Figure 2-25. Added BUFHCE to the Horizontal Clock
Buffer—BUFH, BUFHCE section. Moved Clock Gating for Power Savings.
Updated the MMCMs and PLLs section. Revised the Frequency Synthesis Only Using
Integer Divide section including Figure 3-4. Revised the discussion around adjacent
regions in CLKOUT[0:6] – Output Clocks. Updated the examples after Equation 3-11.
Moved and revised VHDL and Verilog Templates and the Clocking Wizard.
Added Appendix A, Multi-Region Clocking.
05/31/2011 1.2 Added section on 7 Series FPGAs Clocking Differences from Previous FPGA
Generations.
Updated Figure 2-2. Clarified discussion in Clock-Capable Inputs section including
removing Table 1-1: Migration of devices in the same package with different top/bottom
alignments. Redrew Figure 2-4, Figure 2-16, Figure 2-18, and Figure 2-22.
Updated description of CLKOUT[0:6] in Table 3-5. Updated CLKFBSTOPPED –
Feedback Clock Status, page 83. Clarified the MMCM/PLL relationship including
updating Figure 3-10. Added more information to the Phase Shift section, including
Equation 3-5.
Revised Figure A-6 and
Figure A-7. Added Appendix B, Clocking Resources and
Connectivity Variations per Clock Region.
10/27/2011 1.3 Moved 7 Series FPGAs Clocking Differences from Previous FPGA Generations. Added
Clock Buffer Selection Considerations. Clarified description in Clock-Capable Inputs.
Added another note after Figure 2-22, page 53. Added the Stacked Silicon Interconnect
Clocking section.
Updated Figure 3-6, page 73. Clarified descriptions in Frequency Synthesis Using
Fractional Divide in the MMCM, page 73, Interpolated Fine Phase Shift in Fixed or
Dynamic Mode in the MMCM, page 75, Determine the Input Frequency, page 76,
CLKOUT[0:6] – Output Clocks, page 82, and Reference Clock Switching, page 91.
Revised description of STARTUP_WAIT, page 85. Updated RST description in Table 3-5,
page 78. Updated CLKOUT[0]_DIVIDE_F(2) allowed values in Table 3-7, page 83.
Updated Clock Network Deskew, page 72 adding Figure 3-12, page 92.
Updated Table B-1 and added Table B-2.
02/16/2012 1.4 Replaced “clocking backbone” with “clock backbone” and “clocking region” with “clock
region” throughout.
Added Chapter 1, Clocking Overview, containing 7 Series FPGAs Clocking Differences
from Previous FPGA Generations from Chapter 2 and Summary of Clock Connectivity
from Appendix B. Updated Table 1-1. Removed XC7A8, XC7A15, XC7A30T, and
XC7A50T from Table 1-2.
Added Clock-Capable Inputs. Updated Global Clocking Resources, including BUFMR
Primitive. Updated Horizontal Clock Buffer—BUFH, BUFHCE. Updated paragraph
before Figure 2-27.
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