+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; MyOr ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; M2 ; 8 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; M1 ; 8 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
【FPGA】【Verilog】【加法器】半加器和全加器
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2018-03-17
13:31:10
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【FPGA】【Verilog】【加法器】半加器和全加器 （140个子文件） 
_info 2KB _vmake 29B add_full.vpr.ammdb 392B add_full.root_partition.cmp.ammdb 342B add_full.map.ammdb 129B add_full_run_msim_rtl_verilog.do.bak 1KB Add_full_0_delay.vt.bak 580B Add_half_0_delay.vt.bak 502B Add_full_0_delay.v.bak 216B Add_half_0_delay.v.bak 76B My_or.v.bak 27B add_full_run_msim_rtl_verilog.do.bak1 1KB add_full_run_msim_rtl_verilog.do.bak10 1KB add_full_run_msim_rtl_verilog.do.bak11 901B add_full_run_msim_rtl_verilog.do.bak2 1KB add_full_run_msim_rtl_verilog.do.bak3 1KB add_full_run_msim_rtl_verilog.do.bak4 1KB add_full_run_msim_rtl_verilog.do.bak5 1KB add_full_run_msim_rtl_verilog.do.bak6 1KB add_full_run_msim_rtl_verilog.do.bak7 1KB add_full_run_msim_rtl_verilog.do.bak8 1KB add_full_run_msim_rtl_verilog.do.bak9 1KB add_full.cmp.bpm 737B add_full.map.bpm 707B add_full.cmp.cdb 7KB add_full.root_partition.cmp.cdb 4KB add_full.map.cdb 4KB add_full.root_partition.map.cdb 3KB add_full.rtlv_sg.cdb 2KB add_full.map_bb.cdb 2KB add_full.(0).cnf.cdb 2KB add_full.root_partition.map.hbdb.cdb 2KB add_full.(1).cnf.cdb 1KB add_full.rtlv_sg_swap.cdb 827B add_full.(2).cnf.cdb 817B add_full.root_partition.map.reg_db.cdb 222B add_full.db_info 140B add_full.db_info 140B add_full.tiscmp.fastest_slow_1200mv_0c.ddb 116KB add_full.tiscmp.fastest_slow_1200mv_85c.ddb 116KB add_full.tiscmp.slow_1200mv_85c.ddb 115KB add_full.tiscmp.slow_1200mv_0c.ddb 115KB add_full.tiscmp.fast_1200mv_0c.ddb 114KB add_full.asm_labs.ddb 7KB add_full.tis_db_list.ddb 302B add_full.root_partition.cmp.dfp 33B add_full_run_msim_rtl_verilog.do 901B add_full.done 26B add_full.root_partition.map.dpi 881B add_full.root_partition.map.hbdb.hb_info 46B add_full.cmp.hdb 13KB add_full.rrp.hdb 13KB add_full.map.hdb 12KB add_full.pre_map.hdb 12KB add_full.rtlv.hdb 12KB add_full.root_partition.cmp.hdb 12KB add_full.root_partition.map.hbdb.hdb 11KB add_full.map_bb.hdb 11KB add_full.root_partition.map.hdb 11KB add_full.(0).cnf.hdb 999B add_full.(1).cnf.hdb 738B add_full.(2).cnf.hdb 572B add_full.hier_info 1KB add_full.hif 547B add_full.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd 729KB add_full.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd 727KB add_full.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd 723KB
add_full.lpc.html 965B add_full.cmp.idb 1KB modelsim.ini 11KB add_full.jdi 226B add_full_partition_pins.json 1KB add_full.cmp_merge.kpt 210B add_full.root_partition.map.kpt 209B add_full.map.kpt 206B .cmp.kpt 204B add_full.cmp.logdb 15KB add_full.map.logdb 4B add_full.map_bb.logdb 4B add_full.root_partition.cmp.logdb 4B msim_transcript 4KB add_full.pin 33KB _lib.qdb 48KB _lib1_0.qdb 32KB add_full.fit.qmsg 22KB add_full.sta.qmsg 12KB add_full.map.qmsg 7KB add_full.eda.qmsg 6KB prev_cmp_add_full.qmsg 5KB add_full.asm.qmsg 3KB add_full.qpf 1KB _lib1_0.qpg 8KB add_full.qsf 4KB _lib1_0.qtl 18KB add_full.qws 4KB add_full.root_partition.cmp.rcfdb 3KB add_full.cmp.rdb 21KB add_full.sta.rdb 7KB add_full.routing.rdb 5KB add_full.map.rdb 1KB共 140 条
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居然是可以改昵称的
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