TC58NVG0S3HTA00
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TC58NVG0S3HTA00
2012-08-31C
1
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1G BIT (128M 8 BIT) CMOS NAND E
2
PROM
DESCRIPTION
The TC58NVG0S3HTA00 is a single 3.3V 1Gbit (1,140,850,688bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E
2
PROM) organized as (2048 128) bytes 64 pages 1024blocks.
The device has a 2176-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes 8 Kbytes: 2176 bytes 64 pages).
The TC58NVG0S3HTA00 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
x8
Memory cell array 2176 64K 8
Register 2176 8
Page size 2176 bytes
Block size (128K 8K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy
Mode control
Serial input/output
Command control
Number of valid blocks
Min 1004 blocks
Max 1024 blocks
Power supply
V
CC
2.7V to 3.6V
Access time
Cell array to register 25 s max
Serial Read Cycle 25 ns min (CL=50pF)
Program/Erase time
Auto Page Program 300 s/page typ.
Auto Block Erase 2.5 ms/block typ.
Operating current
Read (25 ns cycle) 30 mA max.
Program (avg.) 30 mA max
Erase (avg.) 30 mA max
Standby 50 A max
Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
8 bit ECC for each 512Byte is required.
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资源评论
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guo1593572017-10-27可以！！！！！！！！！一个资源可评论一次
