xilinx vivado xadc IP core code

2014.2: * Version 3.0 (Rev. 4) * Fixed issue with VCCBRAM channel enablement in INIT_48 for sequencer mode 2014.1: * Version 3.0 (Rev. 3) * Internal device family name change, no functional changes * Corrected GUI enablement option in Default sequencer mode 2013.4: * Version 3.0 (Rev. 2) * No changes 2013.3: * Version 3.0 (Rev. 2) * Updated AXI4 Streaming FIFO depth from [1:1017] to [7:1020] * Added check to disable invalid Vauxp/Vauxn pairs for x*7z010clg225 Zynq device * Defined Vp/Vn and Vauxp/Vauxn as bus interfaces, no functional change * Added option in GUI to provide relative path for sim file, no functional change * Added a summary tab in the GUI, no functional change * Added support for Cadence IES and Synopsys VCS simulators * Reduced warnings in synthesis and simulation * Enhanced support for IP Integrator 2013.2: * Version 3.0 (Rev. 1) * Fixed CRITICAL WARNING for clock constraints on DCLK * Updated Life-Cycle status of devices 2013.1: * Version 3.0 * Lower case ports for Verilog * Added AXI4STREAM interface support (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.