MAC芯片LAN91C111 verilog源码

`define LAN_N 4 `define DELAY_US 32'd40 `define BANK_SELECT 4'he // Transmit Control Register /* BANK 0 */ `define TCR_REG 4'h0 // transmit control register `define TCR_ENABLE 16'h0001 // When 1 we can transmit `define TCR_LOOP 16'h0002 // Controls output pin LBK `define TCR_FORCOL 16'h0004 // When 1 will force a collision `define TCR_PAD_EN 16'h0080 // When 1 will pad tx frames < 64 bytes w/0 `define TCR_NOCRC 16'h0100 // When 1 will not append CRC to tx frames `define TCR_MON_CSN 16'h0400 // When 1 tx monitors carrier `define TCR_FDUPLX 16'h0800 // When 1 enables full duplex operation `define TCR_STP_SQET 16'h1000 // When 1 stops tx if Signal Quality Error `define TCR_EPH_LOOP 16'h2000 // When 1 enables EPH block loopback `define TCR_SWFDUP 16'h8000 // When 1 enables Switched Full Duplex mode `define TCR_CLEAR 16'h0 // do NOTHING `define TCR_DEFAULT `TCR_ENABLE //the default settings for the TCR register // EPH Status Register /* BANK 0 */ `define EPH_STATUS_REG 4'h2 `define ES_TX_SUC 16'h0001 // Last TX was successful `define ES_SNGL_COL 16'h0002 // Single collision detected for last tx `define ES_MUL_COL 16'h0004 // Multiple collisions detected for last tx `define ES_LTX_MULT 16'h0008 // Last tx was a multicast `define ES_16COL 16'h0010 // 16 Collisions Reached `define ES_SQET 16'h0020 // Signal Quality Error Test `define ES_LTXBRD 16'h0040 // Last tx was a broadcast `define ES_TXDEFR 16'h0080 // Transmit Deferred `define ES_LATCOL 16'h0200 // Late collision detected on last tx `define ES_LOSTCARR 16'h0400 // Lost Carrier Sense `define ES_EXC_DEF 16'h0800 // Excessive Deferral `define ES_CTR_ROL 16'h1000 // Counter Roll Over indication `define ES_LINK_OK 16'h4000 // Driven by inverted value of nLNK pin `define ES_TXUNRN 16'h8000 // Tx Underrun // Receive Control Register /* BANK 0 */ `define RCR_REG 4'h4 `define RCR_RX_ABORT 16'h0001 // Set if a rx frame was aborted `define RCR_PRMS 16'h0002 // Enable promiscuous mode `define RCR_ALMUL 16'h0004 // When set accepts all multicast frames `define RCR_RXEN 16'h0100 // IFF this is set, we can receive packets `define RCR_STRIP_CRC 16'h0200 // When set strips CRC from rx packets `define RCR_ABORT_ENB 16'h0200 // When set will abort rx on collision `define RCR_FILT_CAR 16'h0400 // When set filters leading 12 bit s of carrier `define RCR_SOFTRST 16'h8000 // resets the chip `define RCR_CLEAR 16'h0 // set it to a base state `define RCR_DEFAULT (`RCR_STRIP_CRC | `RCR_RXEN) // the normal settings for the RCR register // Counter Register /* BANK 0 */ `define COUNTER_REG 4'h6 // Memory Information Register /* BANK 0 */ `define MIR_REG 4'h8 // Receive/Phy Control Register /* BANK 0 */ `define RPC_REG 4'hA `define RPC_SPEED 16'h2000 // When 1 PHY is in 100Mbps mode. `define RPC_DPLX 16'h1000 // When 1 PHY is in Full-Duplex Mode `define RPC_ANEG 16'h0800 // When 1 PHY is in Auto-Negotiate Mode `define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb `define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb `define RPC_LED_100_10 8'h00 // LED = 100Mbps OR's with 10Mbps link detect `define RPC_LED_RES 8'h01 // LED = Reserved `define RPC_LED_10 8'h02 // LED = 10Mbps link detect `define RPC_LED_FD 8'h03 // LED = Full Duplex Mode `define RPC_LED_TX_RX 8'h04 // LED = TX or RX packet occurred `define RPC_LED_100 8'h05 // LED = 100Mbps link dectect `define RPC_LED_TX 8'h06 // LED = TX packet occurred `define RPC_LED_RX 8'h07 // LED = RX packet occurred `define RPC_DEFAULT (`RPC_ANEG | (`RPC_LED_100 << `RPC_LSXA_SHFT) | (`RPC_LED_FD << `RPC_LSXB_SHFT) | `RPC_SPEED | `RPC_DPLX) /* Bank 0 4'hC is reserved */ // Configuration Reg /* BANK 1 */ `define CONFIG_REG 4'h0 `define CONFIG_EXT_PHY 16'h0200 // 1=external MII, 0=internal Phy `define CONFIG_GPCNTRL 16'h0400 // Inverse value drives pin nCNTRL `define CONFIG_NO_WAIT 16'h1000 // When 1 no extra wait states on ISA bus `define CONFIG_EPH_POWER_EN 16'h8000 // When 0 EPH is placed into low power mode. `define CONFIG_DEFAULT (`CONFIG_EPH_POWER_EN) // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low // Base Address Register /* BANK 1 */ `define BASE_REG 4'h2 // Individual Address Registers /* BANK 1 */ `define ADDR0_REG 4'h4 `define ADDR1_REG 4'h6 `define ADDR2_REG 4'h8 // General Purpose Register /* BANK 1 */ `define GP_REG 4'hA // Control Register /* BANK 1 */ `define CTL_REG 4'hc `define CTL_RCV_BAD 16'h4000 // When 1 bad CRC packets are received `define CTL_AUTO_RELEASE 16'h0800 // When 1 tx pages are released automatically `define CTL_LE_ENABLE 16'h0080 // When 1 enables Link Error interrupt `define CTL_CR_ENABLE 16'h0040 // When 1 enables Counter Rollover interrupt `define CTL_TE_ENABLE 16'h0020 // When 1 enables Transmit Error interrupt `define CTL_EEPROM_SELECT 16'h0004 // Controls EEPROM reload & store `define CTL_RELOAD 16'h0002 // When set reads EEPROM into registers `define CTL_STORE 16'h0001 // When set stores registers into EEPROM // MMU Command Register /* BANK 2 */ `define MMU_CMD_REG 4'h0 `define MC_BUSY 1 // When 1 the last release has not completed `define MC_NOP (0<<5) // No Op `define MC_ALLOC (1<<5) // OR with number of 256 byte packets `define MC_RESET (2<<5) // Reset MMU to initial state `define MC_REMOVE (3<<5) // Remove the current rx packet `define MC_RELEASE (4<<5) // Remove and release the current rx packet `define MC_FREEPKT (5<<5) // Release packet in PNR register `define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit `define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs // Packet Number Register /* BANK 2 */ `define PN_REG 4'h2 // Allocation Result Register /* BANK 2 */ `define AR_REG 4'h3 `define AR_FAILED 8'h80 // Alocation Failed // RX FIFO Ports Register /* BANK 2 */ `define RXFIFO_REG 4'h4 // Must be read as a word `define RXFIFO_REMPTY 16'h8000 // RX FIFO Empty // TX FIFO Ports Register /* BANK 2 */ `define TXFIFO_REG `RXFIFO_REG // Must be read as a word `define TXFIFO_TEMPTY 8'h80 // TX FIFO Empty // Pointer Register /* BANK 2 */ `define PTR_REG 4'h6 `define PTR_RCV 16'h8000 // 1=Receive area, 0=Transmit area `define PTR_AUTOINC 16'h4000 // Auto increment the pointer on each access `define PTR_READ 16'h2000 // When 1 the operation is a read // Data Register /* BANK 2 */ `define DATA_REG 4'h8 // Interrupt Status/Acknowledge Register /* BANK 2 */ `define INT_REG 4'hC // Interrupt Mask Register /* BANK 2 */ `define IM_REG 4'hD `define IM_MDINT 8'h80 // PHY MI Register 18 Interrupt `define IM_ERCV_INT 8'h40 // Early Receive Interrupt `define IM_EPH_INT 8'h20 // Set by Etheret Protocol Handler section `define IM_RX_OVRN_INT 8'h10 // Set by Receiver Overruns `define IM_ALLOC_INT 8'h08 // Set when allocation request is completed `define IM_TX_EMPTY_INT 8'h04 // Set if the TX FIFO goes empty `define IM_TX_INT 8'h02 // Transmit Interrrupt `define IM_RCV_INT 8'h01 // Receive Interrupt `define SMC_INTERRUPT_MASK (`IM_EPH_INT | `IM_RX_OVRN_INT | `IM_RCV_INT | `IM_RX_OVRN_INT | `IM_MDINT) // Multicast Table Registers /* BANK 3 */ `define MCAST_REG1 4'h0 `define MCAST_REG2 4'h2 `define MCAST_REG3 4'h4 `define MCAST_REG4 4'h6 // Management Interface Register (MII) /* BANK 3 */ `define MII_REG 4'h8 `define MII_MSK_CRS100 16'h4000 // Disables CRS100 detection during tx half dup `define MII_MDOE 16'h0008 // MII Output Enable `define MII_MCLK 16'h0004 // MII Clock, pin MDCLK `define MII_MDI 16'h0002 // M