TC358749XBG Functional Specification Rev 0.86
749 Functional Spec Confidential Page 1 of 325
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reproduced or used for any purpose other than as needed to support the use of the products of Toshiba Corporation and its affiliates.
TC358749XBG
(H2C+)
Functional Specification
TOSHIBA
TC358749XBG Functional Specification Rev 0.86
749 Functional Spec Confidential Page 2 of 325
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reproduced or used for any purpose other than as needed to support the use of the products of Toshiba Corporation and its affiliates.
1 NOTICE OF DISCLAIMER
2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled
3 by any of the authors or developers of this material or MIPI. The material contained herein is provided on
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749 Functional Spec Confidential Page 3 of 325
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may be disclosed,
reproduced or used for any purpose other than as needed to support the use of the products of Toshiba Corporation and its affiliates.
HISTORY
Revision
Date
Note
Rev 0.72
10/08/13
1. Add 80-pin package, product#749 for HDMI Rx CSI-2Tx (H2C+)
2. Debug registers 0x6500, 0x6504, 0x6508, 0x650C, 0x6510, 0x6514, 0x6518, 0x651C
and 0x6520 all read "0", remove from spec.
3.
Rev 0.73
11/17/2013
1. Updated register fields to remove “??”
2. Typo fixed
3. Removing 0x85A5～0x85AE referring in register bit 0x8520[7] description
4. VPGM and REXT description
Rev 0.76
1/27/2014
1. Add 747 package
2. Add the following registers (description) which the users are recommended Not to
modify their values from those suggested by Toshiba
0x8532, 0x8536, 0x853F
0x85D1
0x8563, 0x8564
0x85AA, 0x85AB, 0x85AF
3. Update default value of register 0x0084 = 0x44
Rev 0.78
5/14/2014
1. Skip 0.77
2. Update I2S Pads Data Lane 0 and Clock from O to IO when used in SLimBus mode
3. Add 1920x1200 support
4. Updated register filed description: 0x5050[2:0], 0x5070[2:0], 0x5090[2:0] and
0x50A0[2:0]
Rev 0.79
5/29/2014
Update scalar related registers
Rev 0.80
8/11/2014
1. Add register 0x861A, audio packet layout register
2. Add HDMI Rx captured video size registers 0x8582/3 (HAct), 0x858/9 (VAct),
0x858A/B (HTotal) and 0x858C/D (VTotal)
3. Correct default value of 0x8840 = 0x80
4. Remove “Draft” watermark
Rev 0.81
11/18/2014
1. Removing referring to VIP scaler (additional) registers and Coefficients in section 6.4
2. Add table titles
3. Update package diagram
Rev 0.82
1/13/2015
Correct note of STBY pin in section 3
Rev 0.83
12/18/2015
Typo Init(O) DAOUT pin in External Pins
Rev 0.84
02/01/2016
Remove 747, Typo fixed register 0x8522, 0x6000
Rev 0.85
13/09/2016
Add comment “for test purpose” to De-Interlace function.
Add weight to package dimension
Rev 0.86
28/09/2016
Add bit to 0x850B,0x851B
TC358749XBG Functional Specification Rev 0.86
749 Functional Spec Confidential Page 4 of 325
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may be disclosed,
reproduced or used for any purpose other than as needed to support the use of the products of Toshiba Corporation and its affiliates.
REFERENCES
1. MIPI D-PHY, “MIPI_D-PHY_specification_v01-00-00, May 14, 2009”
2. MIPI CSI-2, “MIPI Alliance Specification for Display Serial Interface (CSI-2) Version 1.1
Revision 22 Nov 2011”
3. HDMI, “High-Definition Multimedia Interface Specification Version 1.4b March 4, 2010”
4. I2C bus specification, version 2.1, January 2000, Philips Semiconductor
5. IEC 60958, Digital Audio Interface, First Edition, 1999
6. IEC 61937, Digital audio – Interface for non-linear PCM encoded audio bit streams
7. MIPI SlimBus, “MIPI Alliance Specification for Serial Low-power Inter-chip Media Bus
(SLIMbus) Version 1.01.01 – 14 July 2008”
TC358749XBG Functional Specification Rev 0.86
749 Functional Spec Confidential Page 5 of 325
Copyright © 2005-2010 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may be disclosed,
reproduced or used for any purpose other than as needed to support the use of the products of Toshiba Corporation and its affiliates.
Table of content
1 Overview ...................................................................................................................... 20
2 Features ....................................................................................................................... 21
3 External Pins ................................................................................................................ 25
3.1 Pin Summary .......................................................................................................... 27
3.2 Pin Layout .............................................................................................................. 28
4 Major Functional Blocks ............................................................................................. 29
4.1 HDMI-RX ................................................................................................................ 30
4.1.1 3D Support .................................................................................................................. 30
4.1.2 Color Space Conversion (RGB to YCbCr) .................................................................. 30
4.1.2.1 RGB888 to YCbCr422 ......................................................................................... 31
4.1.2.2 RGB888 to YCbCr444 ......................................................................................... 31
4.1.2.3 YCbCr444 to YCbCr422 ...................................................................................... 31
4.1.2.4 YCbCr422 to YCbCr444 ...................................................................................... 31
4.2 Video Processing Module ....................................................................................... 31
4.2.1 De-Interlacer (for test purpose) ................................................................................... 32
4.2.2 Scalar .......................................................................................................................... 32
4.2.3 Color Space Conversion (YCbCr to RGB) .................................................................. 34
4.3 CSI-2 TX Protocol ................................................................................................... 34
4.3.1 CSI-2 TX Interface Block ............................................................................................ 38
4.3.2 CSI-2 TX Packet Format ............................................................................................. 39
4.3.3 Frame Count ............................................................................................................... 40
4.3.4 Checksum Generation ................................................................................................ 40
4.3.5 CSI-2 TX One Frame Operation ................................................................................. 41
4.4 CEC Controller ....................................................................................................... 41
4.4.1 Receive Operation Sequence ..................................................................................... 41
4.4.1.1 Noise cancellation time ....................................................................................... 42
4.4.1.2 Start bit detection................................................................................................. 42
4.4.1.3 Waveform Error Detection ................................................................................... 43
4.4.1.4 Data sampling timing ........................................................................................... 44
4.4.2 Transmit Operation Sequence .................................................................................... 44
4.4.2.1 Wait Time for Bus to be Free .............................................................................. 45
4.4.2.2 Transmission Timing ........................................................................................... 45
4.4.3 Arbitration lost ............................................................................................................. 45
4.4.4 Low level functions ...................................................................................................... 46
4.5 Audio Output Function ............................................................................................ 47
4.5.1 I2S Interface ................................................................................................................ 47
4.5.2 TDM (Time Division Multiplexed) Audio Interface ...................................................... 47
4.5.3 SLIMbus Audio ............................................................................................................ 48
4.5.3.1 SlimBus Clock Generation .................................................................................. 52
4.5.3.1.1 SlimBus Clock from PLL11 or External ActiveFramer ............................................... 52
4.5.3.1.2 SlimBus Clock from HDMI Rx ................................................................................... 53
4.5.4 IEC 60958/61937 over I2S .......................................................................................... 55
4.5.4.1 HBR Split over I2S............................................................................................... 57
4.5.5 Audio PLL LPF Configuration ..................................................................................... 59
4.6 InfraRed (IR) Interface ............................................................................................ 60
4.6.1 Sampling Clock ........................................................................................................... 61
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