verilog通信系统设计书上源码
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2013-01-24
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Verilog通信系统设计.rar （67个子文件） 
Verilog通信系统设计 Verilog源代码 chapter10 11.4节 
SDH_STM1.v 5KB 11.3节 CRC_16_PARALLEL.v 3KB CRC16.v 2KB 11.5节 ENCODE_8B_10B.v 6KB DECODE_8B_10B.v 4KB 11.2节 DESCRAMBLER.v 730B PARALLER_DESCRAMBLER.v 830B SCRAM_TEST.v 978B SCRAMBLER.v 723B PARALLEL_SCRAM_TEST.v 863B PARALLEL_SCRAMBLER.v 925B chapter5 iir_cascade_2.v 2KB fir_lp_8.v 2KB cic_insert_3_2_8_ho.v 2KB iir_filter_8.v 3KB cic_filter_3__28_ho.v 2KB decimate_4.v 807B fir_parr_8.v 3KB insert_4.v 804B chapter8 8.2节 GENSQUE.v 1KB GOLD_SQUE_GEN.v 2KB 8.3节 SPR_SPECTRUM_MOD.v 4KB 8.4节 SERIAL_SOLVE.v 3KB GENSQUE.v.bak 879B SERIAL_TO_PARALLEL.v 2KB SERIAL_SOLVE.v.bak 3KB SERIAL_TO_PARALLEL.v.bak 2KB GATE_CONTROL.v 2KB GENSQUE.v 898B TESTBENCH.v.bak 1KB CATCH_TOP.v 1KB CATCH_TOP.v.bak 1KB GATE_CONTROL.v.bak 2KB TESTBENCH.v 1KB chapter7 CSEEBLOCK.v 12KB KESBLOCK.V 13KB SCBLOCK.V 13KB CONTROLLER.v 16KB RSDECODER.v 3KB RS_ENCODER.V 3KB chapter6 qpsk.v 1KB ppm.v 2KB ask_2.v 768B fsk_2_de.v 1KB ppm_de.v 940B fsk_2.v 947B psk_2.v 962B psk_2_de.v 1KB qpsk_de.v 1KB ask_2_de.v 1KB chapter9 UART_RECEIVER.v 4KB BAUD_GENERATER.v 1KB UART_TRANSMITTER.v 3KB SERIAL_CONTROLLER.v 5KB chapter4 trigger_d.v 606B add_full.v 672B ser_to_parr.v 891B decode3to8.v 917B fifo3.v 4KB count16.v 637B trigger_rs.v 703B trigger_jk.v 699B rom_16_4.v 519B ram_4_4.v 881B mult1from8.v 1KB fre13.v 1KB add_half.v 467B资源评论
