基于vhdl的crc校验码编程

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:59:14 06/11/2011 -- Design Name: -- Module Name: E:/vhdl/crc/crc/tb.vhd -- Project Name: crc -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: crc_code -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_textio.ALL; USE STD.textio.all; ENTITY tb IS END tb; ARCHITECTURE behavior OF tb IS -- Component Declaration COMPONENT crc_code----编码器声明 PORT(clk:in std_logic; rst:in std_logic; din:in std_logic; din_dv:in std_logic; dout:out std_logic; dout_dv:out std_logic); END COMPONENT; COMPONENT frame_receive----帧解析声明 PORT(clk:in std_logic; rst:in std_logic; din:in std_logic; dout:out std_logic; dout_dv:out std_Logic); END COMPONENT; COMPONENT frame------组帧声明 PORT(clk:in std_logic; rst :in std_logic; din :in std_logic; din_dv :in std_logic; dout :out std_logic); END COMPONENT; COMPONENT crc_tx-----检测声明 PORT(clk:in std_logic; rst:in std_logic; din:in std_logic; din_dv:in std_logic; error:out std_logic); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal din : std_logic := '0'; signal din_dv : std_logic := '0'; --Outputs signal error : std_logic:='0'; --temp signal signal cnt:std_logic_vector(5 downto 0):="000000"; signal dout_c_f:std_Logic; signal dout_dv_c_f:std_logic; signal dout_f_fr:std_Logic; signal dout_fr_ct:std_Logic; signal dout_dv_fr_ct:std_logic; signal din_y : std_logic := '0'; signal noise : std_logic := '0'; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; --------------------------------------读取文件 process begin rst <= '1' ; wait for 2 ns; rst <= '0' ; wait ; end process; process(clk) FILE datain : text open read_mode is "din_dv.txt"; VARIABLE fin1 : Line; VARIABLE data_in : STD_LOGIC; begin if(clk'event and clk = '1')then readline (datain,fin1); read (fin1,data_in); din_dv<=data_in; end if; end process; process(clk) FILE datain : text open read_mode is "din.txt"; VARIABLE fin1 : Line; VARIABLE data_in : STD_LOGIC; begin if(clk'event and clk = '1')then readline (datain,fin1); read (fin1,data_in); din_y<=data_in; end if; end process; process(clk) FILE datain : text open read_mode is "noise,txt"; VARIABLE fin1 : Line; VARIABLE data_in : STD_LOGIC; begin if(clk'event and clk = '1')then readline (datain,fin1); read (fin1,data_in); noise<=data_in; end if; end process; din<=noise xor din_y; -------------------------------------连线 u1: crc_code PORT MAP ( clk, rst, din, din_dv, dout_c_f, dout_dv_c_f); u2: frame PORT MAP ( clk, rst, dout_c_f, dout_dv_c_f, dout_f_fr); u3: frame_receive PORT MAP( clk, rst, dout_f_fr, dout_fr_ct, dout_dv_fr_ct); u4: crc_tx PORT MAP ( clk, rst, dout_fr_ct, dout_dv_fr_ct, error); END behavior;