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Release 23A

JEDEC Standard No. 21-C

Page 4.1.2.12.2 – 1

Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules

DDR4 SPD Document Release 2

UDIMM Revision 1.0

RDIMM Revision 1.0

LRDIMM Revision 1.0

1.0 Introduction

This annex describes the serial presence detect (SPD) values for all DDR4 modules. Differences between module types

are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard

document for ‘Specific Features’. The following SPD fields will be documented in the order presented in section 1.1 with

the exception of bytes 128~255 which are documented in separate annexes, one for each family of module types. Further

description of Byte 2 is found in Annex A of the SPD standard.

All unused entries will be coded as 0x00. All unused bits in defined bytes will be coded as 0 except where noted.

DDR4 generation systems are required to check the voltages supported by the DRAMs by reading the SPD and parsing

byte 6, the Module Nominal Voltage, before applying power to the DRAMs. All JEDEC standard modules allow applying

SPD power without applying a supply voltage to the DRAMs in order to support this requirement.

Timing parameters in the SPD represent the operation of the module including all DRAMs and support devices at the

lowest supported supply voltage (see SPD byte 11), and are valid from t

CKAVG

min to t

CKAVG

max (see SPD bytes 18 and

19).

To allow for maximum flexibility as devices evolve, SPD fields described in this document may support device

configuration and timing options that are not included in the JEDEC DDR4 SDRAM data sheet (JESD79-4). Please refer

to DRAM supplier data sheets or JESD79-4 to determine the compatibility of components.

Release 23A

JEDEC Standard No. 21-C

Page 4.1.2.12.2 – 2

1.1 Address map

The following is the SPD address map for all DDR4 modules. It describes where the individual lookup table entries will be

held in the serial EEPROM. Consistent with the definition of DDR4 generation SPD devices, which have four individual

write protection blocks of 128 bytes in length each, the SPD contents are aligned with these blocks as follows:

Block 0: Base Configuration and DRAM Parameters

The following table details the location of each byte in this block.

Block Range Description

0 0~127 0x000~0x07F Base Configuration and DRAM Parameters

1 128~255 0x080~0x0FF Module Specific Parameters -- See subsections L1, L2, and L3 for details

256~319 0x100~0x13F

Reserved -- must be coded as 0x00

320~383 0x140~0x17F Manufacturing Information

3 384~511 0x180~0x1FF End User Programmable

Byte Number

Function Described

Notes

0 0x000 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2

1 0x001 SPD Revision

2 0x002 Key Byte / DRAM Device Type

3 0x003 Key Byte / Module Type

4 0x004 SDRAM Density and Banks 3

5 0x005 SDRAM Addressing 3

6 0x006 SDRAM Package Type 3

7 0x007 SDRAM Optional Features 3

8 0x008 SDRAM Thermal and Refresh Options 3

9 0x009 Other SDRAM Optional Features 3

10 0x00A Reserved -- must be coded as 0x00

11 0x00B Module Nominal Voltage, VDD 3

12 0x00C Module Organization

13 0x00D Module Memory Bus Width

14 0x00E Module Thermal Sensor

15 0x00F Extended module type

16 0x010 Reserved -- must be coded as 0x00

17 0x011 Timebases

18 0x012

SDRAM Minimum Cycle Time (t

CKAVG

min)

19 0x013

SDRAM Maximum Cycle Time (t

CKAVG

max)

20 0x014 CAS Latencies Supported, First Byte 3

21 0x015 CAS Latencies Supported, Second Byte 3

22 0x016 CAS Latencies Supported, Third Byte 3

23 0x017 CAS Latencies Supported, Fourth Byte 3

24 0x018

Minimum CAS Latency Time (t

min)

Note 1 Number of SPD bytes written will typically be programmed as 384 bytes.

Note 2 Size of SPD device will typically be programmed as 512 bytes.

Note 3 From DDR4 SDRAM datasheet.

Note 4 These are optional, in accordance with the JEDEC specification.

Release 23A

JEDEC Standard No. 21-C

Page 4.1.2.12.2 – 3

Block 1: Module Specific Parameters

Bytes 128~255 (0x080~0x0FF) Parameters in this block are specific to the module type as selected by the contents of

SPD Key Byte 3. Refer to the appropriate annex for detailed byte descriptions.

25 0x019

Minimum RAS to CAS Delay Time (t

RCD

min)

26 0x01A

Minimum Row Precharge Delay Time (t

min)

27 0x01B

Upper Nibbles for t

RAS

min and t

min

28 0x01C

Minimum Active to Precharge Delay Time (t

RAS

min), Least Significant Byte

29 0x01D

Minimum Active to Active/Refresh Delay Time (t

min), Least Significant Byte

30 0x01E