ZYNQ7000使用PL+PS实现网络功能的例程xapp1082

************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ � Copyright 2015 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current README.TXT Version: 4.0 Date Last Modified: 08DEC2015 Date Created: 04APR2013 Associated Document: XAPP1082 Supported Device(s): Zynq-7000 AP SOC (45T-FFG900, ZC706 board) ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. 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Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 04APR2013 1.0 Initial Xilinx release. 07JUL2013 2.0 Updated to support PlanAhead 14.6 16DEC2014 3.0 Updated to support Vivado 2014.4 08DEC2015 4.0 Updated to support Vivado 2015.4 SGMII mode support is added to PS-EMIO and PL-ETH designs ========================================================================= 2. OVERVIEW This application note provides four designs- * Use of GEM1 in PS via EMIO with 1000BASE-X/SGMII PHY in PL * Zynq PL Ethernet design with 1000BASE-X/SGMII core a. Zynq PS EMIO Ethernet Here, the GEM1 GMII interface is routed to PL via EMIO. 1000BASE-X/SGMII PHY is used in PL to connect this GMII interface and to SFP module externally to a LAN port. b. Zynq PL Ethernet The programmable logic uses 64-bit HP port to connect to AXI-DMA for high performance data transfer followed by AXI Ethernet IP and 1000BASE-X/SGMII PHY. c. IP Versions used i. AXI-DMA : v7.1 ii. AXI-Ethernet : v6.2 iii. Gigabit Ethernet 1000BASE-X PCS-PMA or SGMII core : v15.3 The Zynq PS EMIO Ethernet design uses only Gigabit Ethernet 1000BASE-X PCS-PMA or SGMII core IP. 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS a. Hardware i. ZC706 Kit ii. Power supply, USB-UART and USB-JTAG cables and Ethernet cable iii. HP 378928-B21 Cisco Gigabit Ethernet RJ45 SFP Module iv. PC system with 1000Mbps capable Ethernet port with preferably Linux OS and netperf installed b. Software i. Vivado Design Suite v2015.4 ii. Linux development PC with ARM GNU cross compile tool chain and Git installed iii. Terminal emulator software like TeraTerm 4. DESIGN FILE HIERARCHY XAPP1082 : Main XAPP folder | |--hardware : Design Sources | | | |--sources : Top level design wrapper | | | |--vivado : Implementation scripts and runs | |--scripts/ps_emio_eth : Contains TCL scripts for running PS EMIO design | |--scripts/pl_eth : Contains TCL scripts for running PL ETH design | |--software | |--devicetree : Contains DTS files for various combinations | | | |--petalinux : Contains petalinux installable BSP, FSBL patch files and | user applications | |--fsbl_patch_files : Contains the files (fsbl_hooks.c, | | sfp.c, si5324.c, i2c_access.c) for designs. | |--ready_to_test : Prebuilt binaries for test | | | |--pl_eth_Cso : SD Card contents for PL Ethernet Design with CSO | | |-- 1000BaseX | | |-- sgmii | | | |--pl_eth_noCso : SD Card contents for PL Ethernet Design without CSO | | |-- 1000BaseX | | |-- sgmii | | | |--ps_emio_eth : SD Card contents for PS GEM EMIO Ethernet Design | | |-- 1000BaseX | | |-- sgmii | | |--README.TXT : the file you are currently reading 5. INSTALLATION AND OPERATING INSTRUCTIONS Please refer to the following link for detailed steps on how to re-build and Hardware and Software. http://www.wiki.xilinx.com/Zynq+PL+Ethernet 6. SUPPORT To obtain technical support for this reference design, go to www.xilinx.com/support to locate answers to known issues in the Xilinx Answers Database or to create a WebCase.