Language File-Name IP Library File-Path
Verilog, processing_system7_bfm_v2_0_arb_wr.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v
Verilog, processing_system7_bfm_v2_0_arb_rd.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v
Verilog, processing_system7_bfm_v2_0_arb_wr_4.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v
Verilog, processing_system7_bfm_v2_0_arb_rd_4.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd_4.v
Verilog, processing_system7_bfm_v2_0_arb_hp2_3.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v
Verilog, processing_system7_bfm_v2_0_arb_hp0_1.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v
Verilog, processing_system7_bfm_v2_0_ssw_hp.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ssw_hp.v
Verilog, processing_system7_bfm_v2_0_sparse_mem.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_sparse_mem.v
Verilog, processing_system7_bfm_v2_0_reg_map.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_reg_map.v
Verilog, processing_system7_bfm_v2_0_ocm_mem.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocm_mem.v
Verilog, processing_system7_bfm_v2_0_intr_wr_mem.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v
Verilog, processing_system7_bfm_v2_0_intr_rd_mem.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v
Verilog, processing_system7_bfm_v2_0_fmsw_gp.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_fmsw_gp.v
Verilog, processing_system7_bfm_v2_0_regc.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_regc.v
Verilog, processing_system7_bfm_v2_0_ocmc.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocmc.v
Verilog, processing_system7_bfm_v2_0_interconnect_model.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_interconnect_model.v
Verilog, processing_system7_bfm_v2_0_gen_reset.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_reset.v
Verilog, processing_system7_bfm_v2_0_gen_clock.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_gen_clock.v
Verilog, processing_system7_bfm_v2_0_ddrc.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ddrc.v
Verilog, processing_system7_bfm_v2_0_axi_slave.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_slave.v
Verilog, processing_system7_bfm_v2_0_axi_master.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_master.v
Verilog, processing_system7_bfm_v2_0_afi_slave.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v
Verilog, processing_system7_bfm_v2_0_processing_system7_bfm.v, system, xil_defaultlib, ../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v
Verilog, system_processing_system7_0_0.v, system, xil_defaultlib, ../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v
Verilog, myip_axi_lite_v1_0_S00_AXI.v, system, xil_defaultlib, ../../../bd/system/ipshared/xilinx.com/myip_axi_lite_v1_0/hdl/myip_axi_lite_v1_0_S00_AXI.v
Verilog, myip_axi_lite_v1_0.v, system, xil_defaultlib, ../../../bd/system/ipshared/xilinx.com/myip_axi_lite_v1_0/hdl/myip_axi_lite_v1_0.v
Verilog, system_myip_axi_lite_0_0.v, system, xil_defaultlib, ../../../bd/system/ip/system_myip_axi_lite_0_0/sim/system_myip_axi_lite_0_0.v
VHDL, cdc_sync.vhd, system, lib_cdc_v1_0_2, ../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd
VHDL, upcnt_n.vhd, system, proc_sys_reset_v5_0_8, ../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd
VHDL, sequence_psr.vhd, system, proc_sys_reset_v5_0_8, ../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd
VHDL, lpf.vhd, system, proc_sys_reset_v5_0_8, ../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd
VHDL, proc_sys_reset.vhd, system, proc_sys_reset_v5_0_8, ../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd
VHDL, system_rst_processing_system7_0_100M_0.vhd, system, xil_defaultlib, ../../../bd/system/ip/system_rst_processing_system7_0_100M_0/sim/system_rst_processing_system7_0_100M_0.vhd
Verilog, generic_baseblocks_v2_1_carry_and.v, system, generic_baseblocks_v2_1_0, ../../../ipstatic/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_and.v
Verilog, generic_baseblocks_v2_1_carry_latch_and.v, system, generic_baseblocks_v2_1_0, ../../../ipstatic/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_and.v
Verilog, generic_baseblocks_v2_1_carry_latch_or.v, system, generic_baseblocks_v2_1_0, ../../../ipstatic/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_or.v
Verilog, generic_baseblocks_v2_1_carry_or.v, system, generic_base
ZYNQ AXI总线PL/PS间通信的例程代码 （908个子文件） 
30df37f0bd3b001617aaaaad5a64ff7e 2KB 408cdd56b83b001617aaaaad5a64ff7e 0B 5043d7e5b83b001617aaaaad5a64ff7e 2KB 9090d914b93b001617aaaaad5a64ff7e 2KB libxil.a 856KB a005e0fcb83b001617aaaaad5a64ff7e 2KB runme.bat 229B runme.bat 229B system.bd 35KB system_wrapper.bit 3.86MB system_wrapper.bit 3.86MB system.bxml 4KB ps7_init.c 561KB ps7_init.c 561KB ps7_init_gpl.c 560KB ps7_init_gpl.c 560KB xadcps.c 54KB xdmaps.c 52KB xqspips.c 49KB xil_cache.c 46KB xusbps_endpoint.c 42KB xsdps.c 42KB xemacps_control.c 40KB xemacps_bdring.c 37KB xdevcfg.c 29KB xsdps_options.c 28KB xgpiops_intr.c 25KB xuartps_options.c 24KB xscugic.c 24KB xuartps.c 21KB xgpiops.c 21KB xil_testmem.c 20KB xscugic_hw.c 18KB xemacps.c 17KB xil_misc_psreset_api.c 16KB xuartps_intr.c 14KB xqspips_options.c 14KB xusbps_intr.c 14KB xttcps.c 13KB xusbps.c 12KB _profile_timer_hw.c 12KB xemacps_intr.c 10KB xil_io.c 10KB xdevcfg_intr.c 9KB xil_printf.c 9KB xil_testcache.c 9KB xil_exception.c 9KB xscutimer.c 8KB xil_testio.c 8KB xadcps_intr.c 8KB xpm_counter.c 8KB xttcps_options.c 7KB xscuwdt.c 7KB xscugic_intr.c 7KB xqspips_hw.c 7KB xil_mmu.c 6KB xuartps_selftest.c 6KB xgpiops_hw.c 6KB xuartps_hw.c 6KB xl2cc_counter.c 6KB xcoresightpsdcc.c 5KB xil_assert.c 5KB vectors.c 5KB xemacps_hw.c 5KB xscutimer_selftest.c 5KB profile_cg.c 5KB xqspips_selftest.c 5KB xgpiops_selftest.c 5KB xdevcfg_hw.c 4KB xadcps_selftest.c 4KB xscuwdt_selftest.c 4KB xusbps_hw.c 4KB xtime_l.c 4KB xdmaps_hw.c 4KB xdevcfg_selftest.c 4KB xscugic_selftest.c 4KB xscugic_sinit.c 4KB xdmaps_selftest.c 4KB xplatform_info.c 4KB xgpiops_sinit.c 4KB xsdps_sinit.c 4KB xscutimer_sinit.c 4KB xttcps_selftest.c 4KB xemacps_sinit.c 4KB xttcps_sinit.c 4KB xscuwdt_sinit.c 4KB xadcps_sinit.c 4KB xuartps_sinit.c 4KB xqspips_sinit.c 4KB xusbps_sinit.c 3KB xdmaps_sinit.c 3KB xdevcfg_sinit.c 3KB _profile_init.c 3KB usleep.c 3KB write.c 3KB read.c 3KB sleep.c 3KB profile_hist.c 2KB _sbrk.c 2KB sbrk.c 2KB共 908 条
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资源评论
stayoyo2019-03-28米联的代码
好的呢大玲2019-03-19还不错，有一定的参考价值
fcc2008
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- 资源: 242
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