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Application Report

SPRA375E - October 2004

Using the TMS320VC5503/VC5507/VC5509/VC5509A

Bootloader

Clay Turner

Muhammad Haque

C5000 Application

ABSTRACT

This document describes the features of the on-chip bootloader provided with the

TMS320VC5503/VC5507/VC5509/VC5509A digital signal processor (DSP). Included are

descriptions of each of the available boot modes and any interfacing requirements

associated with them as well as instructions on generating the boot table.

Contents

1 Introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Bootloader Features 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 On-Chip ROM Description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Bootloader Operation 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Bootloader Initialization 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Boot Mode Selection 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Boot Mode Options 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Direct Execution From External Asynchronous Memory 7 . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Parallel EMIF Boot Mode 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 EHPI Boot Mode 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Standard Serial Boot Mode 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.5 SPI EEPROM Boot Mode 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6 I2C EEPROM Boot Mode (VC5503/VC5507/VC5509/VC5509A Only) 15 . . . . . . . . . . .

2.3.7 USB Boot Mode 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 IO4 Behavior 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 The Boot Table 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 DSP Resources Used by the Bootloader 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 The Boot Table Structure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 Register Configuration and Delay During Boot 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 Code and Data Sections in the Boot Table 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.5 Creating the Boot Table 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Debugging Bootloader Issues 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Direct Execution from External Asynchronous Memory 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Parallel EMIF Boot Mode 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Host Port Interface Boot Mode 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Standard Serial Boot Mode 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 SPI EEPROM Boot Mode 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 I2C EEPROM Boot Mode 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 UART Boot Mode 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Trademarks are the property of their respective owners.

SPRA375E

Using the TMS320VC5503/VC5507/VC5509/VC5509A Bootloader

4 References 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Figures

Figure 1. EHPI Wait Flag and Entry-Point Address 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2. McBSP0 Receive Data Format for Bootload (16-bit shown) 10 . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3. IO4 Latency for Boot Table Programmed Delays 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4. Signal Connections for SPI EEPROM Boot Mode 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 5. SPI EEPROM Mode Transfer Protocol With 16-Bit Addresses 13 . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6. SPI EEPROM Mode Transfer Protocol With 24-Bit Addresses 14 . . . . . . . . . . . . . . . . . . . . . . . .

Figure 7. Signal Connections for I2C EEPROM Boot Mode 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 8. Reading the First Byte in a 64Kbyte Block 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 9. Current Address Read Command 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 10. Boot Table Structure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table 1. TMS320VC5503/VC5507/VC5509/VC5509A ROM Memory Map 4 . . . . . . . . . . . . . . . . . . . . . . .

Table 2. Bootloader Initialization 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3. Boot Mode Selection Options 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4. Boot Mode Types for the Hex Conversion Utility 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Examples

Example 1. Creating the Boot Table for Application my_app.out to Boot From 16-Bit External Asyn-

chronous Memory 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example 2. Creating the Boot Table for Application my_app.out to Boot Mode From 8-Bit Standard

Serial Mode 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Introduction

This section provides a description of the features of the on-chip bootloader provided with the

TMS320VC5503/VC5507/VC5509/VC5509A digital signal processor (DSP). All references in

this document to VC5503/VC5507/VC5509/VC5509A refer to both the

TMX320VC5503/VC5507/VC5509/VC5509A and TMS320VC5503/VC5507/VC5509/VC5509A,

unless otherwise specified.

1.1 Bootloader Features

The VC5503/VC5507/VC5509/VC5509A bootloader is used to transfer code from an external

source into internal or external program memory following power-up. This allows the code to

reside in slow non-volatile memory externally, and be transferred to high-speed memory to be

executed.

To accommodate different system requirements, the VC5503/VC5507/VC5509/VC5509A offers

a variety of different boot modes. The following is a list of the different boot modes implemented

by the bootloader, and a summary of their functional operation:

SPRA375E

Using the TMS320VC5503/VC5507/VC5509/VC5509A Bootloader

• Boot from the Enhanced Host Port Interface (EHPI)

The code to be executed is loaded into on-chip memory by an external host processor via

the EHPI following reset. Code execution begins when the host indicates to the CPU that the

application has been loaded. EHPI boot can be performed with the EHPI, configured as

multiplexed or non-multiplexed. The operation of this mode is described in section 2.3.3.

• Parallel EMIF boot from 16-bit external asynchronous memory

The bootloader reads the boot table from the external memory interface (EMIF), configured

for asynchronous memory. The boot table contains the code or data sections to be loaded,

the destination addresses for each of the sections, the execution address once loading is

completed, and other configuration information. The operation of this mode is described in

section 2.3.2.

• Standard serial boot through McBSP0 (8- or 16-bit supported)

The bootloader receives the boot table from the McBSP0, operating in standard mode, and

loads the code according to the information specified in the boot table. The operation of this

mode is described in section 2.3.4.

• SPI EEPROM serial boot though McBSP0

The bootloader receives the boot table from the McBSP0 operating in SPI mode, and loads

the code according to the information specified in the boot table. The data can be received

from an SPI-format serial EEPROM, or from another SPI-compliant serial port. The

bootloader supports SPI EEPROMs based on 16- or 24-bit addresses. The operation of this

mode is described in section 2.3.5.

• Universal Serial Bus (USB) boot

The bootloader receives the boot table through the on-chip USB peripheral. The protocol

supported conforms to the USB standard and the data is loaded to a bulk end-point. The

operation of this mode is described in section 2.3.7.

• Bootloading from I2C interface

The boot loader reads the boot table from an I2C slave device (EEPROM) and loads the

code according to the information specified in the boot table.

The bootloader also offers the following features:

• Pin-controlled boot mode selection

A subset of the general-purpose input/output (I/O) pins is used to select the boot mode. The

boot mode selection process is discussed in section 2.2.

• Selectable entry point

The desired entry point (the first address of execution after the boot load is complete) is

programmable, and is stored in the boot table. The boot table is discussed in section 2.5.

• Port-addressed register configuration during boot

Port-addressed registers (such as those used to control peripherals) can be configured

during the boot load, providing the ability to modify the clock generator, reconfigure the EMIF

strobe timings, or preset peripheral register values. The address and contents of the register

to be modified are contained in the boot table. This capability is discussed in section 2.5.3.

• Programmable delay during boot

Programmable delays of up to 65535 CPU clock cycles can be added during the register

configuration process, to ensure that new configurations are complete before the boot

process continues. This capability is discussed in section 2.5.3.

SPRA375E

Using the TMS320VC5503/VC5507/VC5509/VC5509A Bootloader

1.2 On-Chip ROM Description

On the VC5503/VC5507/VC5509/VC5509A, the on-chip ROM contains several

factory-programmed sections including:

• Bootloader program (described in this document)

• 256-word sine look-up table, consisting of 256 signed Q15 integers representing

360 degrees.

• Factory test code, used by TI for testing the device.

• Interrupt vector table.

The ROM memory map is shown in Table 1.

Table 1. TMS320VC5503/VC5507/VC5509/VC5509A ROM Memory Map

Starting Byte Address Contents

FF_0000h USB bootloader components

†

FF_8000h Main bootloader code

FF_FA00h Sine table

FF_FC00h Factory test code

FF_FF00h Interrupt vector table

FF_FFFCh ID code

†

USB bootmode option is not available on VC5503

2 Bootloader Operation

The following sections describe the structure and operation of the production

VC5503/VC5507/VC5509/VC5509A bootloader.

2.1 Bootloader Initialization

When the VC5503/VC5507/VC5509/VC5509A bootloader begins execution, the program

performs some initialization of the VC5503/VC5507/VC5509/VC5509A prior to loading code.

The VC5503/VC5507/VC5509/VC5509A resources that are configured by the bootloader are

described in Table 2.

SPRA375E

Using the TMS320VC5503/VC5507/VC5509/VC5509A Bootloader

Table 2. Bootloader Initialization

Resource Initialization Value

Stack registers The data stack register (SP) is initialized to address 000090h, and the system stack register

(SSP) is initialized to address 000080h.

Stack configuration The stack configuration is set to the default mode of 32-bit stack, with slow return.

Interrupts The INTM bit of Status Register 1 (ST1_55) is set to the default value of 1, to disable

interrupts.

Memory-mapped

registers

Two words are reserved for temporary storage of the entry-point address at 000060h and

000061h.

Sign extension The SXMD bit of Status Register 1 (ST1_55) is cleared to 0, to disable sign-extension mode.

After the bootloader copies all of the sections, SXMD is set back to 1, before execution is

transferred to the application.

Compatibility mode

The 54CM bit of Status Register 1 (ST1_55) is set to 1, to enable compatibility mode during

and after the bootload.

After the initialization is performed, the bootloader loads the on-chip RAM according to the boot

mode selected, and then causes the VC5503/VC5507/VC5509/VC5509A to begin execution of

the loaded code. At that point, the bootload process is complete. Whenever the system is reset,

the VC5503/VC5507/VC5509/VC5509A starts execution of the bootloader again, and the entire

bootload process is repeated.

The remaining sections of this document describe the various boot modes and boot tables in

detail.

2.2 Boot Mode Selection

The desired boot mode is selected by setting the four boot mode select pins BOOTM[0:3].

These pins are sampled after reset when the bootloader program begins execution. The

BOOTM pins are shared with the general-purpose I/O (GPIO) pins.

• BOOTM3 is shared with IO0.

• BOOTM2 is shared with IO3.

• BOOTM1 is shared with IO2.

• BOOTM0 is shared with IO1.

Another GPIO pin, IO4, is used as an output for handshaking purposes on some of the boot

modes. Although this pin is not involved in boot-mode selection, you should be aware that this

pin will become active as an output during the bootload process, and should design accordingly.

After the bootload is complete, the loaded application may change the function of IO[4:0] pins.

The available boot mode options and their corresponding BOOTM pin configurations are shown

in Table 3. Some configurations are reserved for the addition of future boot modes, and should

not be selected.

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Father恩恩

2013-06-27

挺好使的谢谢
sbfkpyud

2015-12-22

下载后用不了。
LGX0123456

2014-06-11

tms320f240PQA试一下
deterShao

2019-04-25

挺好的，谢谢

blackmailer

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