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Arm1176jzfs (ARM11 芯片文档)
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Copyright © 2004-2009 ARM Limited. All rights reserved.
ARM DDI 0301H (ID012310)
ARM1176JZF-S
™
Revision: r0p7
Technical Reference Manual
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ii
ID012310 Non-Confidential, Unrestricted Access
ARM1176JZF-S
Technical Reference Manual
Copyright © 2004-2009 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with
®
or
™
are registered trademarks or trademarks of ARM
®
Limited in the EU and other
countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may
be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any
loss or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Figure 14-1 on page 14-2 reprinted with permission from IEEE Std. 1149.1-2001, IEEE Standard Test Access Port and
Boundary-Scan Architecture by IEEE Std. The IEEE disclaims any responsibility or liability resulting from the
placement and use in the described manner.
Some material in this document is based on IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std
754-1985. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described
manner
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Unrestricted Access is an ARM internal classification.
Change history
Date Issue Confidentiality Change
19 July 2004 A Non-Confidential First release.
18 April 2005 B Non-Confidential Minor corrections and enhancements.
29 June 2005 C Non-Confidential r0p1 changes, addition of CPUCLAMP
Figure 10-1 updated.
Section 10.4.3 updated.
Table 23-1 updated.
Minor corrections and enhancements.
22 March 2006 D Non-Confidential Update for r0p2. Minor corrections and enhancements.
19 July 2006 E Non-Confidential Patch update for r0p4.
19 April 2007 F Non-Confidential Update for r0p6 release. Minor corrections and enhancements.
15 February 2008 G Non-Confidential Update for r0p7 release. Minor corrections and enhancements.
27 November 2009 H Non-Confidential Update for r0p7 maintenance release. Minor corrections and enhancements.
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. iii
ID012310 Non-Confidential, Unrestricted Access
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. iv
ID012310 Non-Confidential, Unrestricted Access
Contents
ARM1176JZF-S Technical Reference Manual
Preface
About this book ........................................................................................................ xxii
Feedback ................................................................................................................ xxvi
Chapter 1 Introduction
1.1 About the processor ................................................................................................. 1-2
1.2 Extensions to ARMv6 .............................................................................................. 1-3
1.3 TrustZone security extensions ................................................................................. 1-4
1.4 ARM1176JZF-S architecture with Jazelle technology ............................................. 1-6
1.5 Components of the processor .................................................................................. 1-8
1.6 Power management ............................................................................................... 1-23
1.7 Configurable options .............................................................................................. 1-25
1.8 Pipeline stages ...................................................................................................... 1-26
1.9 Typical pipeline operations .................................................................................... 1-28
1.10 ARM1176JZF-S instruction set summary .............................................................. 1-32
1.11 Product revisions ................................................................................................... 1-47
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ............................................................................... 2-2
2.2 Secure world and Non-secure world operation with TrustZone ............................... 2-3
2.3 Processor operating states .................................................................................... 2-12
2.4 Instruction length ................................................................................................... 2-13
2.5 Data types .............................................................................................................. 2-14
2.6 Memory formats ..................................................................................................... 2-15
2.7 Addresses in a processor system .......................................................................... 2-16
2.8 Operating modes ................................................................................................... 2-17
2.9 Registers ................................................................................................................ 2-18
2.10 The program status registers ................................................................................. 2-24
2.11 Additional instructions ............................................................................................ 2-30
Contents
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. v
ID012310 Non-Confidential, Unrestricted Access
2.12 Exceptions ............................................................................................................. 2-36
2.13 Software considerations ........................................................................................ 2-59
Chapter 3 System Control Coprocessor
3.1 About the system control coprocessor ..................................................................... 3-2
3.2 System control processor registers ....................................................................... 3-13
Chapter 4 Unaligned and Mixed-endian Data Access Support
4.1 About unaligned and mixed-endian support ............................................................ 4-2
4.2 Unaligned access support ....................................................................................... 4-3
4.3 Endian support ......................................................................................................... 4-6
4.4 Operation of unaligned accesses .......................................................................... 4-13
4.5 Mixed-endian access support ................................................................................ 4-17
4.6 Instructions to reverse bytes in a general-purpose register ................................... 4-20
4.7 Instructions to change the CPSR E bit .................................................................. 4-21
Chapter 5 Program Flow Prediction
5.1 About program flow prediction ................................................................................. 5-2
5.2 Branch prediction ..................................................................................................... 5-4
5.3 Return stack ............................................................................................................. 5-7
5.4 Memory Barriers ...................................................................................................... 5-8
5.5 ARM1176JZF-S IMB implementation .................................................................... 5-10
Chapter 6 Memory Management Unit
6.1 About the MMU ........................................................................................................ 6-2
6.2 TLB organization ...................................................................................................... 6-4
6.3 Memory access sequence ....................................................................................... 6-7
6.4 Enabling and disabling the MMU ............................................................................. 6-9
6.5 Memory access control .......................................................................................... 6-11
6.6 Memory region attributes ....................................................................................... 6-14
6.7 Memory attributes and types ................................................................................. 6-20
6.8 MMU aborts ........................................................................................................... 6-27
6.9 MMU fault checking ............................................................................................... 6-29
6.10 Fault status and address ....................................................................................... 6-34
6.11 Hardware page table translation ............................................................................ 6-36
6.12 MMU descriptors .................................................................................................... 6-43
6.13 MMU software-accessible registers ....................................................................... 6-53
Chapter 7 Level One Memory System
7.1 About the level one memory system ........................................................................ 7-2
7.2 Cache organization .................................................................................................. 7-3
7.3 Tightly-coupled memory .......................................................................................... 7-7
7.4 DMA ....................................................................................................................... 7-10
7.5 TCM and cache interactions .................................................................................. 7-12
7.6 Write buffer ............................................................................................................ 7-16
Chapter 8 Level Two Interface
8.1 About the level two interface .................................................................................... 8-2
8.2 Synchronization primitives ....................................................................................... 8-6
8.3 AXI control signals in the processor ........................................................................ 8-8
8.4 Instruction Fetch Interface transfers ...................................................................... 8-14
8.5 Data Read/Write Interface transfers ...................................................................... 8-15
8.6 Peripheral Interface transfers ................................................................................ 8-37
8.7 Endianness ............................................................................................................ 8-38
8.8 Locked access ....................................................................................................... 8-39
Chapter 9 Clocking and Resets
9.1 About clocking and resets ........................................................................................ 9-2
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