Document Number: MD00103
Revision 2.02
January 5, 2004
MIPS Technologies, Inc.
1225 Charleston Road
Mountain View, CA 94043-1353
Copyright © 2000-2003 MIPS Technologies Inc. All rights reserved.
MIPS32 4KE™ Processor Core Family Software
User’s Manual
Copyright © 2000-2003 MIPS Technologies, Inc. All rights reserved.
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MIPS32 4KE™ Processor Core Family Software User’s Manual, Revision 2.02
Copyright © 2000-2003 MIPS Technologies Inc. All rights reserved.
Template: B1.10, Built with tags: 2B EMERALD MIPS32 PROC
MIPS32 4KE™ Processor Core Family Software User’s Manual, Revision 2.02 i
Copyright © 2000-2003 MIPS Technologies Inc. All rights reserved.
Table of Contents
Chapter 1 Introduction to the MIPS32™ 4KE™ Processor Core Family ............................................................................1
1.1 The 4KEc™, 4KEm™, and 4KEp™ Cores ............................................................................................................1
1.2 Features ...................................................................................................................................................................2
1.3 4KE™ Core Block Diagram ...................................................................................................................................4
1.3.1 Required Logic Blocks .................................................................................................................................5
1.3.2 Optional Logic Blocks ..................................................................................................................................8
Chapter 2 Pipeline of the 4KE™ Core ................................................................................................................................13
2.1 Pipeline Stages ......................................................................................................................................................13
2.1.1 I Stage: Instruction Fetch ............................................................................................................................15
2.1.2 E Stage: Execution ......................................................................................................................................15
2.1.3 M Stage: Memory Fetch .............................................................................................................................15
2.1.4 A Stage: Align .............................................................................................................................................15
2.1.5 W Stage: Writeback ....................................................................................................................................16
2.2 Instruction Cache Miss ..........................................................................................................................................16
2.3 Data Cache Miss ...................................................................................................................................................16
2.4 Multiply/Divide Operations ..................................................................................................................................17
2.5 MDU Pipeline (4KEc™ and 4KEm™ Cores) ......................................................................................................17
2.5.1 32x16 Multiply (4KEc™ & 4KEm™ Cores) .............................................................................................20
2.5.2 32x32 Multiply (4KEc ™ & 4KEm™ Cores) .............................................................................................20
2.5.3 Divide (4KEc™ & 4KEm™ Cores) ...........................................................................................................21
2.6 MDU Pipeline (4KEp™ Core) ..............................................................................................................................22
2.6.1 Multiply (4KEp™ Core) .............................................................................................................................23
2.6.2 Multiply Accumulate (4KEp™ Core) ........................................................................................................23
2.6.3 Divide (4KEp™ Core) ................................................................................................................................23
2.7 Branch Delay .........................................................................................................................................................24
2.8 Data Bypassing .....................................................................................................................................................24
2.8.1 Load Delay ..................................................................................................................................................25
2.8.2 Move from HI/LO and CP0 Delay ..............................................................................................................26
2.9 Coprocessor 2 instructions ....................................................................................................................................26
2.10 Interlock Handling ..............................................................................................................................................27
2.11 Slip Conditions ....................................................................................................................................................28
2.12 Instruction Interlocks ..........................................................................................................................................29
2.13 Hazards ................................................................................................................................................................30
2.13.1 Types of Hazards ......................................................................................................................................30
2.13.2 Instruction Listing .....................................................................................................................................32
2.13.3 Eliminating Hazards ..................................................................................................................................33
Chapter 3 Memory Management of the 4KE™ Core .........................................................................................................34
3.1 Introduction ...........................................................................................................................................................34
3.2 Modes of Operation ..............................................................................................................................................35
3.2.1 Virtual Memory Segments ..........................................................................................................................36
3.2.2 User Mode ...................................................................................................................................................38
3.2.3 Kernel Mode ...............................................................................................................................................39
3.2.4 Debug Mode ................................................................................................................................................41
3.3 Translation Lookaside Buffer (4KEc™ Core Only) .............................................................................................43
3.3.1 Joint TLB ....................................................................................................................................................43
3.3.2 Instruction TLB ...........................................................................................................................................46
3.3.3 Data TLB ....................................................................................................................................................46
3.4 Virtual-to-Physical Address Translation (4KEc™ Core) .....................................................................................46
3.4.1 Hits, Misses, and Multiple Matches ............................................................................................................48
ii MIPS32 4KE™ Processor Core Family Software User’s Manual, Revision 2.02
Copyright © 2000-2003 MIPS Technologies Inc. All rights reserved.
3.4.2 Memory Space ............................................................................................................................................49
3.4.3 TLB Instructions .........................................................................................................................................50
3.5 Fixed Mapping MMU (4KEm™ & 4KEp™ Cores) ............................................................................................51
3.6 System Control Coprocessor .................................................................................................................................53
Chapter 4 Exceptions and Interrupts in the 4KE™ Core ....................................................................................................54
4.1 Exception Conditions ............................................................................................................................................54
4.2 Exception Priority .................................................................................................................................................55
4.3 Interrupts ...............................................................................................................................................................56
4.3.1 Interrupt Modes ...........................................................................................................................................56
4.3.2 Generation of Exception Vector Offsets for Vectored Interrupts ...............................................................64
4.4 GPR Shadow Registers .........................................................................................................................................65
4.5 Exception Vector Locations ..................................................................................................................................66
4.6 General Exception Processing ..............................................................................................................................67
4.7 Debug Exception Processing ................................................................................................................................69
4.8 Exceptions .............................................................................................................................................................70
4.8.1 Reset Exception ..........................................................................................................................................70
4.8.2 Soft Reset Exception ...................................................................................................................................71
4.8.3 Debug Single Step Exception .....................................................................................................................72
4.8.4 Debug Interrupt Exception ..........................................................................................................................73
4.8.5 Non-Maskable Interrupt (NMI) Exception .................................................................................................73
4.8.6 Machine Check Exception (4KEc™ core) .................................................................................................74
4.8.7 Interrupt Exception .....................................................................................................................................74
4.8.8 Debug Instruction Break Exception ............................................................................................................74
4.8.9 Watch Exception — Instruction Fetch or Data Access ..............................................................................75
4.8.10 Address Error Exception — Instruction Fetch/Data Access .....................................................................75
4.8.11 TLB Refill Exception — Instruction Fetch or Data Access (4KEc™ core only) ....................................76
4.8.12 TLB Invalid Exception — Instruction Fetch or Data Access (4KEc™ core only) ..................................77
4.8.13 Bus Error Exception — Instruction Fetch or Data Access .......................................................................77
4.8.14 Debug Software Breakpoint Exception ....................................................................................................78
4.8.15 Execution Exception — System Call ........................................................................................................78
4.8.16 Execution Exception — Breakpoint .........................................................................................................78
4.8.17 Execution Exception — Reserved Instruction ..........................................................................................78
4.8.18 Execution Exception — Coprocessor Unusable .......................................................................................79
4.8.19 Execution Exception — Coprocessor 2 Exception ...................................................................................79
4.8.20 Execution Exception — Implementation-Specific 1 exception ................................................................79
4.8.21 Execution Exception — Implementation Specific 2 exception ................................................................80
4.8.22 Execution Exception — Integer Overflow ...............................................................................................80
4.8.23 Execution Exception — Trap ....................................................................................................................80
4.8.24 Debug Data Break Exception ....................................................................................................................81
4.8.25 TLB Modified Exception — Data Access (4KEc™ core only) ...............................................................81
4.9 Exception Handling and Servicing Flowcharts .....................................................................................................82
Chapter 5 CP0 Registers of the 4KE™ Core ......................................................................................................................89
5.1 CP0 Register Summary .........................................................................................................................................90
5.2 CP0 Register Descriptions ....................................................................................................................................92
5.2.1 Index Register (CP0 Register 0, Select 0) ...................................................................................................93
5.2.2 Random Register (CP0 Register 1, Select 0) ..............................................................................................94
5.2.3 EntryLo0 and EntryLo1 Registers (CP0 Registers 2 and 3, Select 0) .........................................................95
5.2.4 Context Register (CP0 Register 4, Select 0) ...............................................................................................97
5.2.5 PageMask Register (CP0 Register 5, Select 0) ...........................................................................................98
5.2.6 PageGrain Register (CP0 Register 5, Select 1) ........................................................................................100
5.2.7 Wired Register (CP0 Register 6, Select 0) ................................................................................................101
5.2.8 HWREna Register (CP0 Register 7, Select 0) ..........................................................................................102
5.2.9 BadVAddr Register (CP0 Register 8, Select 0) .........................................................................................103
5.2.10 Count Register (CP0 Register 9, Select 0) ..............................................................................................104
MIPS32 4KE™ Processor Core Family Software User’s Manual, Revision 2.02 iii
Copyright © 2000-2003 MIPS Technologies Inc. All rights reserved.
5.2.11 EntryHi Register (CP0 Register 10, Select 0) .........................................................................................105
5.2.12 Compare Register (CP0 Register 11, Select 0) .......................................................................................106
5.2.13 Status Register (CP0 Register 12, Select 0) ............................................................................................107
5.2.14 IntCtl Register (CP0 Register 12, Select 1) ............................................................................................112
5.2.15 SRSCtl Register (CP0 Register 12, Select 2) ..........................................................................................114
5.2.16 SRSMap Register (CP0 Register 12, Select 3) ........................................................................................117
5.2.17 Cause Register (CP0 Register 13, Select 0) ............................................................................................118
5.2.18 Exception Program Counter (CP0 Register 14, Select 0) .......................................................................122
5.2.19 Processor Identification (CP0 Register 15, Select 0) ..............................................................................123
5.2.20 EBase Register (CP0 Register 15, Select 1) ...........................................................................................124
5.2.21 Config Register (CP0 Register 16, Select 0) ...........................................................................................125
5.2.22 Config1 Register (CP0 Register 16, Select 1) .........................................................................................127
5.2.23 Config2 Register (CP0 Register 16, Select 2) .........................................................................................129
5.2.24 Config3 Register (CP0 Register 16, Select 3) .........................................................................................130
5.2.25 Load Linked Address (CP0 Register 17, Select 0) .................................................................................132
5.2.26 WatchLo Register (CP0 Register 18, Select 0-7) ....................................................................................133
5.2.27 WatchHi Register (CP0 Register 19, Select 0-7) ....................................................................................134
5.2.28 Debug Register (CP0 Register 23, Select 0) ...........................................................................................136
5.2.29 Trace Control Register (CP0 Register 23, Select 1) ...............................................................................139
5.2.30 Trace Control2 Register (CP0 Register 23, Select 2) .............................................................................142
5.2.31 User Trace Data Register (CP0 Register 23, Select 3) ..........................................................................144
5.2.32 TraceBPC Register (CP0 Register 23, Select 4) .....................................................................................145
5.2.33 Debug Exception Program Counter Register (CP0 Register 24, Select 0) .............................................146
5.2.34 ErrCtl Register (CP0 Register 26, Select 0) ...........................................................................................147
5.2.35 TagLo Register (CP0 Register 28, Select 0) ...........................................................................................148
5.2.36 DataLo Register (CP0 Register 28, Select 1) .........................................................................................149
5.2.37 ErrorEPC (CP0 Register 30, Select 0) ...................................................................................................150
5.2.38 DeSave Register (CP0 Register 31, Select 0) .........................................................................................151
Chapter 6 Hardware and Software Initialization of the 4KE™ Core ................................................................................153
6.1 Hardware-Initialized Processor State ..................................................................................................................153
6.1.1 Coprocessor 0 State ...................................................................................................................................153
6.1.2 TLB Initialization (4KEc™ core only) .....................................................................................................154
6.1.3 Bus State Machines ...................................................................................................................................154
6.1.4 Static Configuration Inputs .......................................................................................................................154
6.1.5 Fetch Address ............................................................................................................................................154
6.2 Software Initialized Processor State ...................................................................................................................154
6.2.1 Register File ..............................................................................................................................................154
6.2.2 TLB (4KEc™ Core Only) ........................................................................................................................154
6.2.3 Caches .......................................................................................................................................................155
6.2.4 Coprocessor 0 State ...................................................................................................................................155
Chapter 7 Caches of the 4KE™ Core ...............................................................................................................................158
7.1 Cache Configurations ..........................................................................................................................................158
7.2 Cache Protocols ...................................................................................................................................................160
7.2.1 Cache Organization ...................................................................................................................................160
7.2.2 Cacheability Attributes .............................................................................................................................161
7.2.3 Replacement Policy ..................................................................................................................................161
7.2.4 Virtual Aliasing .........................................................................................................................................162
7.3 Instruction Cache ................................................................................................................................................163
7.4 Data Cache ..........................................................................................................................................................163
7.5 CACHE Instruction .............................................................................................................................................164
7.6 Software Cache Testing ......................................................................................................................................165
7.6.1 I-Cache/D-cache Tag Arrays ....................................................................................................................165
7.6.2 I-Cache Data Array ...................................................................................................................................165
7.6.3 I-Cache WS Array .....................................................................................................................................165
