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Reference Guide

Graphics Core Next Architecture, Generation 3

March 2015

Revision 1.0

DISCLAIMER

The information contained herein is for informational purposes only, and is subject to

change without notice. While every precaution has been taken in the preparation of this

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AMD GRAPHICS C ORE N EXT T ECHNOLOGY

iii

Contents

Preface

Chapter 1

Introduction

Chapter 2

Program Organization

2.1 The Compute Shader Program Type ............................................................................................. 2-1

2.2 Instruction Terminology .................................................................................................................. 2-2

2.3 Data Sharing ..................................................................................................................................... 2-3

2.3.1 Local Data Share (LDS) .................................................................................................. 2-4

2.3.2 Global Data Share (GDS)................................................................................................ 2-5

2.4 Device Memory................................................................................................................................. 2-5

Chapter 3

Kernel State

3.1 State Overview ................................................................................................................................. 3-1

3.2 Program Counter (PC) .................................................................................................................... 3-2

3.3 EXECute Mask .................................................................................................................................. 3-2

3.4 Status Registers............................................................................................................................... 3-2

3.5 Mode Register .................................................................................................................................. 3-4

3.6 GPRs and LDS.................................................................................................................................. 3-5

3.6.1 Out-of-Range Behavior ................................................................................................... 3-5

3.6.2 SGPR Allocation and Storage........................................................................................ 3-6

3.6.3 SGPR Alignment.............................................................................................................. 3-6

3.6.4 VGPR Allocation and Alignment.................................................................................... 3-6

3.6.5 LDS Allocation and Clamping........................................................................................ 3-6

3.7 M# Memory Descriptor .................................................................................................................... 3-7

3.8 SCC: Scalar Condition Code........................................................................................................... 3-7

3.9 Vector Compares: VCC and VCCZ.................................................................................................. 3-8

3.10 Trap and Exception Registers ........................................................................................................ 3-8

3.11 Memory Violations ......................................................................................................................... 3-10

Chapter 4

AMD GRAPHICS C ORE N EXT T ECHNOLOGY

Program Flow Control

4.1 Program Control............................................................................................................................... 4-1

4.2 Branching.......................................................................................................................................... 4-1

4.3 Work-Groups..................................................................................................................................... 4-2

4.4 Data Dependency Resolution ......................................................................................................... 4-2

4.5 Manually Inserted Wait States (NOPs) .......................................................................................... 4-4

4.6 Arbitrary Divergent Control Flow................................................................................................... 4-5

Chapter 5

Scalar ALU Operations

5.1 SALU Instruction Formats .............................................................................................................. 5-1

5.2 Scalar ALU Operands ...................................................................................................................... 5-2

5.3 Scalar Condition Code (SCC) ......................................................................................................... 5-2

5.4 Integer Arithmetic Instructions....................................................................................................... 5-5

5.5 Conditional Instructions.................................................................................................................. 5-5

5.6 Comparison Instructions................................................................................................................. 5-6

5.7 Bit-Wise Instructions ....................................................................................................................... 5-6

5.8 Special Instructions ......................................................................................................................... 5-8

Chapter 6

Vector ALU Operations

6.1 Microcode Encodings...................................................................................................................... 6-1

6.2 Operands........................................................................................................................................... 6-2

6.2.1 Instruction Inputs ............................................................................................................ 6-2

6.2.2 Instruction Outputs ......................................................................................................... 6-3

6.2.3 Out-of-Range GPRs......................................................................................................... 6-5

6.3 Instructions....................................................................................................................................... 6-5

6.4 Denormalized and Rounding Modes ............................................................................................. 6-7

6.5 ALU CLAMP Bit Usage.................................................................................................................... 6-7

6.6 VGPR Indexing ................................................................................................................................. 6-7

6.6.1 Indexing Instructions ...................................................................................................... 6-8

6.6.2 Special Cases .................................................................................................................. 6-8

Chapter 7

Scalar Memory Operations

7.1 Microcode Encoding........................................................................................................................ 7-1

7.2 Operations......................................................................................................................................... 7-2

7.2.1 S_LOAD_DWORD ............................................................................................................ 7-2

7.2.2 S_STORE_DWORD.......................................................................................................... 7-2

7.2.3 S_BUFFER_LOAD_DWORD, S_BUFFER_STORE_DWORD........................................ 7-2

7.2.4 S_DCACHE_INV, S_DCACHE_WB ................................................................................. 7-3

7.2.5 S_MEM_TIME ................................................................................................................... 7-3

7.2.6 S_MEM_REALTIME.......................................................................................................... 7-3

AMD GRAPHICS C ORE N EXT T ECHNOLOGY

7.3 Dependency Checking..................................................................................................................... 7-3

7.4 Alignment and Bounds Checking .................................................................................................. 7-3

Chapter 8

Vector Memory Operations

8.1 Vector Memory Buffer Instructions................................................................................................ 8-1

8.1.1 Simplified Buffer Addressing......................................................................................... 8-2

8.1.2 Buffer Instructions .......................................................................................................... 8-2

8.1.3 VGPR Usage .................................................................................................................... 8-4

8.1.4 Buffer Data ....................................................................................................................... 8-5

8.1.5 Buffer Addressing ........................................................................................................... 8-6

Range Checking8-8

Swizzled Buffer Addressing8-8

Proposed Uses Cases for Swizzled Addressing8-10

8.1.6 Alignment ........................................................................................................................8-11

8.1.7 Buffer Resource .............................................................................................................8-11

8.1.8 Memory Buffer Load to LDS ....................................................................................... 8-12

Clamping Rules8-13

8.1.9 GLC Bit Explained......................................................................................................... 8-13

8.2 Vector Memory (VM) Image Instructions..................................................................................... 8-14

8.2.1 Image Instructions ........................................................................................................ 8-15

8.2.2 Image Opcodes with No Sampler................................................................................ 8-16

8.2.3 Image Opcodes with Sampler...................................................................................... 8-17

8.2.4 VGPR Usage .................................................................................................................. 8-19

8.2.5 Image Resource............................................................................................................. 8-20

8.2.6 Sampler Resource......................................................................................................... 8-21

8.2.7 Data Formats ................................................................................................................. 8-23

8.2.8 Vector Memory Instruction Data Dependencies........................................................ 8-24

Chapter 9

Flat Memory Instructions

9.1 Flat Memory Instructions ................................................................................................................ 9-1

9.2 Instructions....................................................................................................................................... 9-2

9.2.1 Ordering............................................................................................................................ 9-3

9.2.2 Important Timing Consideration.................................................................................... 9-3

9.3 Addressing........................................................................................................................................ 9-3

9.4 Memory Error Checking .................................................................................................................. 9-3

9.5 Data.................................................................................................................................................... 9-4

9.6 Scratch Space (Private)................................................................................................................... 9-4

Chapter 10

Data Share Operations

10.1 Overview.......................................................................................................................................... 10-1

10.2 Dataflow in Memory Hierarchy ..................................................................................................... 10-2