ddr3_device_operation_timing_diagram_rev14-2.pdf

DDR3 SDRAM的时序图，供学习调用DDR3使用。 目录 DDR3 SDRAM Specification 1. Functional Description ..................................................................................................................................................5 1.1 Simplified State Diagram ......................................................................................................................................... 5 1.2 Basic Functionality................................................................................................................................................... 6 1.3 RESET and Initialization Procedure ........................................................................................................................ 6 1.3.1. Power-up Initialization Sequence..................................................................................................................... 6 1.3.2. Reset Initialization with Stable Power .............................................................................................................. 7 1.4 Register Definition ................................................................................................................................................... 8 1.4.1. Programming the Mode Registers ................................................................................................................... 8 1.4.2. Mode Register MR0 ......................................................................................................................................... 9 1.4.2.1 Burst Length, Type and Order .................................................................................................................... 9 1.4.2.2 CAS Latency............................................................................................................................................... 10 1.4.2.3 Test Mode................................................................................................................................................... 10 1.4.2.4 DLL Reset................................................................................................................................................... 10 1.4.2.5 Write Recovery ........................................................................................................................................... 10 1.4.2.6 Precharge PD DLL...................................................................................................................................... 10 1.4.3. Mode Register MR1 ......................................................................................................................................... 11 1.4.3.1 DLL Enable/Disable .................................................................................................................................... 12 1.4.3.2 Output Driver Impedance Control ............................................................................................................... 12 1.4.3.3 ODT Rtt Values........................................................................................................................................... 12 1.4.3.4 Additive Latency (AL).................................................................................................................................. 12 1.4.3.5 Write leveling .............................................................................................................................................. 12 1.4.3.6 Output Disable ............................................................................................................................................ 12 1.4.3.7 TDQS, TDQS.............................................................................................................................................. 13 1.4.4. Mode Register MR2 ......................................................................................................................................... 14 1.4.4.1 Partial Array Self-Refresh (PASR).............................................................................................................. 15 1.4.4.2 CAS Write Latency (CWL) .......................................................................................................................... 15 1.4.4.3 Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT) ................................................................ 15 1.4.4.4 Dynamic ODT (Rtt_WR) ............................................................................................................................. 15 1.4.5. Mode Register MR3 ......................................................................................................................................... 15 1.4.5.1 Multi-Purpose Register (MPR).................................................................................................................... 15 2. DDR3 SDRAM Command Description and Operation.............

VESA-DSC-1.2a.pdf

Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Intellectual Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Support for this Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Acknowledgments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Section 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1 Document Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.2 Display Stream Compression Objectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3 Display Stream Compression Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.4 Acronyms, Initialisms, and Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.6 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6.1 Bit Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6.2 Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.7 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.8 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Section 2 Requirements (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Section 3 Theory of Operation (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.2 Color Space Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3 Prediction and Quantization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.1 Modified Median-Adaptive Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.2 Block Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3.3 Midpoint Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.4 Indexed Color History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.5 Bitstream Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.5.1 Substream Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.5.2 Substream Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.6 Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.7 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.7.1 Hypothetical Reference Decoder-Based Timing Model . . . . . . . . . . . . . . . . . .39 3.7.2 Constant and Variable Bit Rate Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7.3 Slices and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.8 Options for Slices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.9 Slice Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46VESA Display Stream Compression (DSC) Standard UNAUTHORIZED DISTRIBUTION PROHIBITED Version 1.2a Copyright © 2014 – 2017 V

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This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in any form or by any means without the prior written permission of Digilent, Inc. DIGILENT and the Digilent logo are registered trademarks of Digilent, Inc. All trademarks and trade names are the properties of their respective owners and Digilent, Inc. disclaims any proprietary interest or right in trademarks, service marks and trade names other than its own. Digilent is not responsible for typographical or other errors or omissions or for direct, indirect, incidental or consequential damages related to this material or resulting from its use. Digilent makes no warranty or representation respecting this material, which is provided on an "AS IS" basis. DIGILENT HEREBY DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, INCLUDING, WITHOUT LIMITATION, REPRESENTATIONS REGARDING ACCURACY AND COMPLETENESS, ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, SUITABILITY OR FITNESS FOR A PARTICULAR PURPOSE, TITLE AND/OR NON-INFRINGEMENT. This material is not designed, intended or authorized for use in medical, life support, life sustaining or nuclear applications or applications in which the failure of the product could result in personal injury, death or property damage. Any party using or selling products for use in any such applications do so at their sole risk and agree that Digilent is not liable, in whole or in part, for any claim or damage arising from such use, and agree to fully indemnify, defend and hold harmless Digilent from and against any and all claims, damages, loss, cost, expense or liability arising out of or in connection with the use or performance of products in such applications.

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