multi-channel DDR

multi-channel memory architecture

LPDDR5 协议 （Low Power Double Data Rate 5）

LPDDR5 SDRAM is a high-speed synchronous SDRAM device internally configured with 1 channel containing either 16 or 8 DQ signals. The bank architecture is user-selectable, and can be either eight banks (8B Mode), four banks with four bank groups (BG Mode), or sixteen banks (16B Mode). See 2.2.3 for more information.

DDR DFI 5.0 version

主要是针对DDR5/LPDDR5 Controller/PHY对接的接口协议，标准的DFI 5.0协议；

DFI_v3_1_specification

DFI标准协议，版本为3.1.The DDR PHY Interface (DFI) is an interface protocol that defines the signals, timing parameters, and programmable parameters required to transfer control information and data across the DFI, and between the MC and the PHY.

相关的RSICV开源架构

RISC-V架构作为一种指令集架构，在介绍细节之前，让我们先了解设计的哲学。所谓设计的“哲学”便是其推崇的一种策略，譬如说我们熟知的日本车的设计哲学是经济省油，美国车的设计哲学是霸气外漏等。RISC-V架构的设计哲学是什么呢？是“大道至简”。