• dm8107 dvr rdk 硬件手册

    dm8107 dvr rdk开发板的硬件手册。

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    98
    1.28MB
    2015-10-10
    15
  • evm8168参考板原理图

    evm8168参考板原理图,orcad格式的,可以直接做硬件设计

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    66
    3.04MB
    2015-10-09
    9
  • dm8168 dvr_rdr原理图

    ti公司的dm8168 dvr rev08参考设计最新的原理图

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    199
    1.07MB
    2015-10-09
    10
  • dm385 ipnc的原理图

    ti公司tms320dm385 ipnc参考板的原理图。

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    88
    225KB
    2015-10-09
    9
  • cpci express的标准

    目前能找到的cpci express总线的标准

    5
    408
    5.62MB
    2015-10-09
    50
  • CPCI_E背板设计与仿真

    CPCI_E背板设计与仿真的文档介绍

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    365
    1.49MB
    2015-10-09
    50
  • pex8112数据手册

    pex8112芯片的数据手册,官网最新下载的

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    583
    2.87MB
    2015-10-09
    50
  • RS Decoder

    ++++++++++++++++++++++++++ RS Decoder (31,19,6) v1.1 ++++++++++++++++++++++++++ This project consists of 8 verilog files including a testbench file. The files are: - RSDecoder.v : contains description of top module of the decoder. It combines 5 modules of typical RS Decoder building blocks. - scblock.v : contains description of the SC (Syndrome Computation) block and its submodules. - kesblock.v : KES (Key Equation Solver) block and its submodules. - cseeblock.v : CSEE (Chien Search and Error Evaluator) block and parallel invers multiplier module. CSEE is the only block in the decoder that use invers multiplier to compute error magnitude using Fourney Formula. - controller.v : describes controller module. It consists of 2 FSMs and 2 counters. - fifo_register.v : a FIFO register consists of 31 registers to store received word and a register to synchronize outputted data with CSEE block. - common_modules.v: this file contains basic modules that used by other higher modules. It behaves like a library for the project. - testbench.v : the testbench contains 3 different received word vectors. First received word contains no error symbol. Second word contains 6 error symbols and the last word contains 8 error symbols. Limitations in this version: Despite its high data rates, the decoder has some limitations that must be considered. - It flags decoding failure at the end of outputted word. So, other block outside the decoder cannot differentiate between uncorrected word and corrected word until it receive decoding failure flag at the end of the word. - Decoding failure is detected when degree of error location polynomial and number of its roots is not equal. It means the error location polynomial doesn't have roots in the underlying GF(2^5). To determine the roots, decoder must activate CSEE block first. Hence, decoding failure is detected after all elements in GF(2^5) have been evaluated. - Uncorrectable word still have to be summed with wrong error values. Because decoding failure is detected at the end of word, there is no other mechanism to solve the problem, unless decoder start to output the word after all GF(2^5) elements has been evaluated. Hopefully, in next version, limitations above can be solved. Rudy Dwi Putra rudy.dp@gmail.com

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    246
    13KB
    2010-06-08
    43
  • spi master

    spi控制器的verilog实现,编译通过,测试使用没有问题

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    61
    30KB
    2010-06-08
    9
  • pcr分析与pcr分析测量指南

    pcr测量指南,对于做pcr分析很有帮助

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    66
    3.02MB
    2009-01-19
    6
  • 阅读者勋章

    授予在CSDN APP累计阅读博文达到3天的你,是你的坚持与努力,使你超越了昨天的自己。
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