高速差分线性接收器（可用于逻辑分析仪等数字仪器前级隔离比较器）
Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard Operate With a Single 3.3-V Supply Designed for Signaling Rate of up to 400 Mbps Differential Input Thresholds ±100 mV Max Typical Propagation Delay Time of 2.1 ns Power Dissipation 60 mW Typical Per Receiver at 200 MHz Bus-Terminal ESD Protection Exceeds 8 kV Low-Voltage TTL (LVTTL) Logic Output Levels Pin Compatible With AM26LS32, MC3486, and μA9637 Open-Circuit Fail-Safe
0
372
911KB
2010-09-14
50
