s3c2410_datasheet

Architecture · Integrated system for hand-held devices and general embedded applications · 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core · Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux · Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance · ARM920T CPU core supports the ARM debug architecture. · Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB)

S3C44B0_datasheet

S3C44B0资料手册 SAMSUNG's S3C44B0X 16/32-bit RISC microprocessor is designed to provide a cost-effective and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C44B0X also provides the following: 8KB cache, optional internal SRAM, LCD controller, 2-channel UART with handshake, 4- channel DMA, System manager (chip select logic, FP/ EDO/SDRAM controller), 5-channel timers with PWM, I/O ports, RTC, 8-channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, Sync. SIO interface and PLL for clock.

S3C2440_datasheet

S3C2440芯片资料文档 INTRODUCTION This user’s manual describes SAMSUNG's S3C2440A 16/32-bit RISC microprocessor. SAMSUNG’s S3C2440A is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440A includes the following components.

dm9000a的datasheet资料

1. General Description............................................................................................................6 2. Block Diagram ...................................................................................................................6 3. Feature................................................................................................................................7 4. Pin Configuration...............................................................................................................8 4.1 Pin Configuration I: 16-bit mode..................................................................................................8 4.2 Pin Configuration II: 8-bit mode..................................................................................................9 5. Pin Description..................................................................................................................10 5.1 Processor Interface.................................................................................................................10 5.1.1 8-bit mode ........................................................................................................................10 5.2 EEPROM Interface................................................................................................................11 5.3 Clock Interface.....................................................................................................................11 5.4 LED Interface.......................................................................................................................11 5.5 10/100 PHY/Fiber..................................................................................................................11 5.6 Miscellaneous.......................................................................................................................12 5.7 Power Pins..........................................................................................................................12 5.8 strap pins table ......................................................................................................................12 6. Vendor Control and Status Register Set.............................................................................13 6.1Network Control Register (00H)...................................................................................................14 6.2 Network Status Register (01H)...................................................................................................15 6.3 TX Control Register (02H)........................................................................................................15 6.4 TX Status Register I ( 03H ) for packet index I................................................................................15 6.5 TX Status Register II ( 04H ) for packet index I I..............................................................................16 6.6 RX Control Register ( 05H ).......................................................................................................16 6.7 RX Status Register ( 06H ).........................................................................................................16