mastering_reactive_slaves.pdf
UVM slave agent example
create_power_domain的-define_func_type, addressing_the_challenges_of_generically_specifying_power_intent_with_multi_rail_macros.pdf
Optimum sleep transistor design and implementation are critical to a successful power-gating design. This paper describes a number of critical considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency
Verification Methodology Manual for Low Power (VMM-LP) 2009
Low_power_Methodology_manual_for_system_on_chip_design