C2000 adc_SOC
This example sets up the PLL in x12/2 mode. For 60 MHz devices (default) (assuming a 10Mhz input clock). Interrupts are enabled and the ePWM1 is setup to generate a periodic ADC SOC - ADCINT1. Two channels are converted, ADCINA4 and ADCINA2.
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2014-03-19
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