RTL-to-Gates Synthesis using Synopsys Design Compiler

RTL-to-Gates Synthesis using Synopsys Design Compiler

StateCAD 教程

StateCAD 教程，帮助大家可以快速入门

Introduction to ASICs

The difference between full-custom and semicustom ASICs • The difference between standard-cell, gate-array, and programmable ASICs • ASIC design flow • Design economics • ASIC cell library