PCI Local Bus
Specification
Revision 2.2
December 18, 1998
Revision 2.2
ii
REVISION REVISION HISTORY DATE
1.0 Original issue 6/22/92
2.0 Incorporated connector and expansion board specification 4/30/93
2.1 Incorporated clarifications and added 66 MHz chapter 6/1/95
2.2 Incorporated ECNs and improved readability 12/18/98
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Copyright © 1992, 1993, 1995, 1998 PCI Special Interest Group
Revision 2.2
iii
Contents
Chapter 1 Introduction
1.1. Specification Contents............................................................................................................ 1
1.2. Motivation .............................................................................................................................. 1
1.3. PCI Local Bus Applications ................................................................................................... 2
1.4. PCI Local Bus Overview........................................................................................................ 3
1.5. PCI Local Bus Features and Benefits..................................................................................... 4
1.6. Administration........................................................................................................................ 6
Chapter 2 Signal Definition
2.1. Signal Type Definition ........................................................................................................... 8
2.2. Pin Functional Groups............................................................................................................ 8
2.2.1. System Pins ..................................................................................................................... 8
2.2.2. Address and Data Pins..................................................................................................... 9
2.2.3. Interface Control Pins.................................................................................................... 10
2.2.4. Arbitration Pins (Bus Masters Only)............................................................................. 11
2.2.5. Error Reporting Pins...................................................................................................... 12
2.2.6. Interrupt Pins (Optional) ............................................................................................... 13
2.2.7. Additional Signals ......................................................................................................... 15
2.2.8. 64-Bit Bus Extension Pins (Optional) ........................................................................... 17
2.2.9. JTAG/Boundary Scan Pins (Optional) .......................................................................... 18
2.3. Sideband Signals .................................................................................................................. 19
2.4. Central Resource Functions.................................................................................................. 19
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Chapter 3 Bus Operation
3.1. Bus Commands..................................................................................................................... 21
3.1.1. Command Definition.....................................................................................................21
3.1.2. Command Usage Rules ................................................................................................. 23
3.2. PCI Protocol Fundamentals.................................................................................................. 26
3.2.1. Basic Transfer Control .................................................................................................. 26
3.2.2. Addressing..................................................................................................................... 27
3.2.2.1. I/O Space Decoding................................................................................................ 28
3.2.2.2. Memory Space Decoding ....................................................................................... 28
3.2.2.3. Configuration Space Decoding............................................................................... 30
3.2.3. Byte Lane and Byte Enable Usage ................................................................................ 38
3.2.4. Bus Driving and Turnaround......................................................................................... 39
3.2.5. Transaction Ordering and Posting................................................................................. 40
3.2.5.1. Transaction Ordering and Posting for Simple Devices .......................................... 41
3.2.5.2. Transaction Ordering and Posting for Bridges....................................................... 42
3.2.6. Combining, Merging, and Collapsing ........................................................................... 44
3.3. Bus Transactions .................................................................................................................. 46
3.3.1. Read Transaction........................................................................................................... 47
3.3.2. Write Transaction .......................................................................................................... 48
3.3.3. Transaction Termination ............................................................................................... 49
3.3.3.1. Master Initiated Termination.................................................................................. 49
3.3.3.2. Target Initiated Termination .................................................................................. 52
3.3.3.3. Delayed Transactions ............................................................................................. 61
3.4. Arbitration ............................................................................................................................ 68
3.4.1. Arbitration Signaling Protocol ...................................................................................... 70
3.4.2. Fast Back-to-Back Transactions.................................................................................... 72
3.4.3. Arbitration Parking........................................................................................................ 74
3.5. Latency ................................................................................................................................. 75
3.5.1. Target Latency............................................................................................................... 75
3.5.1.1. Target Initial Latency ............................................................................................. 75
3.5.1.2. Target Subsequent Latency .................................................................................... 77
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v
3.5.2. Master Data Latency...................................................................................................... 78
3.5.3. Memory Write Maximum Completion Time Limit ...................................................... 78
3.5.4. Arbitration Latency ....................................................................................................... 79
3.5.4.1. Bandwidth and Latency Considerations................................................................. 80
3.5.4.2. Determining Arbitration Latency ........................................................................... 82
3.5.4.3. Determining Buffer Requirements ......................................................................... 87
3.6. Other Bus Operations ........................................................................................................... 88
3.6.1. Device Selection............................................................................................................ 88
3.6.2. Special Cycle................................................................................................................. 90
3.6.3. Address/Data Stepping ..................................................................................................91
3.6.4. Interrupt Acknowledge..................................................................................................93
3.7. Error Functions..................................................................................................................... 93
3.7.1. Parity Generation........................................................................................................... 94
3.7.2. Parity Checking ............................................................................................................. 95
3.7.3. Address Parity Errors .................................................................................................... 95
3.7.4. Error Reporting.............................................................................................................. 95
3.7.4.1. Data Parity Error Signaling on PERR# .................................................................. 96
3.7.4.2. Other Error Signaling on SERR# ........................................................................... 97
3.7.4.3. Master Data Parity Error Status Bit........................................................................ 98
3.7.4.4. Detected Parity Error Status Bit ............................................................................. 98
3.7.5. Delayed Transactions and Data Parity Errors ............................................................... 98
3.7.6. Error Recovery .............................................................................................................. 99
3.8. 64-Bit Bus Extension.......................................................................................................... 100
3.8.1. Determining Bus Width During System Initialization ................................................ 104
3.9. 64-bit Addressing ............................................................................................................... 105
3.10. Special Design Considerations......................................................................................... 108
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