SAED_PDK90nm.rar

SAED_PDK90 - 90nm Process Design Kit

© 2009-2016 SYNOPSYS ARMENIA Educational Department Rev. 1.12 Page 1 of 52

PROCESS DESIGN KIT

SAED_PDK90

DATABOOK

Revision : 1.12

Technology : SAED90nm

SAED_PDK90 - 90nm Process Design Kit

© 2009-2016 SYNOPSYS ARMENIA Educational Department Rev. 1.12 Page 2 of 52

CONTENTS

1 Introduction ............................................................................................................................... 7

3 SAED_PDK90 ........................................................................................................................ 10

3.1 Technology files ............................................................................................................ 10

3.1.1 Display resources ................................................................................................ 10

3.1.2 Technology file .................................................................................................... 10

3.1.3 Layer map file ...................................................................................................... 10

3.2 Physical verification files ................................................................................................ 10

3.2.1 Hercules .............................................................................................................. 10

3.3 Parasitic extract files ...................................................................................................... 11

3.3.1 STARRCXT ......................................................................................................... 11

4 Support devices ...................................................................................................................... 12

4.7 Varactors ....................................................................................................................... 16

5 Device Datasheets ................................................................................................................. 17

5.1 NMOS Transistor ........................................................................................................... 17

5.1.1 nmos3t ................................................................................................................. 17

5.1.2 nmos4t ................................................................................................................. 18

5.1.3 nmos4t_25 ........................................................................................................... 19

5.1.4 nmos4t_hvt .......................................................................................................... 21

5.1.5 nmos4t_lvt ........................................................................................................... 22

5.2 PMOS Transistor ........................................................................................................... 23

5.2.1 pmos3t ................................................................................................................. 23

5.3.2 rppoly ................................................................................................................... 32

5.3.3 rnpoly_wos .......................................................................................................... 33

5.3.4 rppoly_wos .......................................................................................................... 34

5.3.5 rndiff ..................................................................................................................... 36

5.3.6 rpdiff ..................................................................................................................... 37

5.4 Capacitor ....................................................................................................................... 38

5.4.1 ccap ..................................................................................................................... 38

SAED_PDK90 - 90nm Process Design Kit

© 2009-2016 SYNOPSYS ARMENIA Educational Department Rev. 1.12 Page 3 of 52

5.5 Diode ............................................................................................................................. 40

5.5.1 nd......................................................................................................................... 40

5.5.2 pd......................................................................................................................... 41

5.8.1 nvar...................................................................................................................... 48

5.8.2 pvar...................................................................................................................... 49

6 References ............................................................................................................................. 52

SAED_PDK90 - 90nm Process Design Kit

© 2009-2016 SYNOPSYS ARMENIA Educational Department Rev. 1.12 Page 4 of 52

LIST OF TABLES

Table 1.1 Content of SAED_PDK90 ............................................................................................. 7

Table 4.6 Capacitor symbol parameters ..................................................................................... 14

Table 4.7 Diode Spice models list .............................................................................................. 14

Table 4.8 Diode symbol parameters ........................................................................................... 14

Table 4.9 BJT Spice models list ................................................................................................. 15

Table 4.10 BJT symbol parameters ............................................................................................ 15

Table 4.11 Inductor Spice models list ......................................................................................... 15

Table 4.12 Inductor symbol parameters ..................................................................................... 16

Table 4.13 Varactor Spice models list ........................................................................................ 16

Table 4.14 Varactor symbol parameters ..................................................................................... 16

Table 5.1 nmos3t Spice model ................................................................................................... 17

Table 5.8 nmos4t LVS Checking ................................................................................................ 19

Table 5.9 nmos4t_25 Spice model ............................................................................................. 19

Table 5.10 nmos4t_25 Device Layers ........................................................................................ 20

Table 5.11 nmos4t_25 Device Derivation ................................................................................... 20

Table 5.12 nmos4t_25 LVS Checking ........................................................................................ 20

Table 5.13 nmos4t_hvt Spice model .......................................................................................... 21

Table 5.14 nmos4t_hvt Device Layers ....................................................................................... 21

Table 5.15 nmos4t_hvt Device Derivation .................................................................................. 22

Table 5.16 nmos4t_hvt LVS Checking ....................................................................................... 22

Table 5.17 nmos4t_lvt Spice model ............................................................................................ 22

Table 5.24 pmos3t LVS Checking .............................................................................................. 24

Table 5.25 pmos4t Spice model ................................................................................................. 25

Table 5.26 pmos4t Device Layers .............................................................................................. 25

Table 5.27 pmos4t Device Derivation ......................................................................................... 26

Table 5.28 pmos4t LVS Checking .............................................................................................. 26

Table 5.29 pmos4t_25 Spice model ........................................................................................... 26

Table 5.30 pmos4t_25 Device Layers ........................................................................................ 27

SAED_PDK90 - 90nm Process Design Kit

© 2009-2016 SYNOPSYS ARMENIA Educational Department Rev. 1.12 Page 5 of 52

Table 5.31 pmos4t_25 Device Derivation ................................................................................... 27

Table 5.32 pmos4t_25 LVS Checking ........................................................................................ 27

Table 5.33 pmos4t_hvt Spice model .......................................................................................... 28

Table 5.40 pmos4t_lvt LVS Checking ......................................................................................... 30

Table 5.41 rnpoly Spice model ................................................................................................... 31

Table 5.42 rnpoly Device Layers ................................................................................................ 31

Table 5.43 rnpoly Device Derivation ........................................................................................... 31

Table 5.44 rnpoly LVS Checking ................................................................................................ 31

Table 5.45 rppoly Spice model ................................................................................................... 32

Table 5.46 rppoly Device Layers ................................................................................................ 32

Table 5.47 rppoly Device Derivation ........................................................................................... 33

Table 5.48 rppoly LVS Checking ................................................................................................ 33

Table 5.49 rnpoly_wos Spice model ........................................................................................... 33

Table 5.56 rppoly_wos LVS Checking ........................................................................................ 35

Table 5.57 rndiff Spice model ..................................................................................................... 36

Table 5.58 rndiff Device Layers .................................................................................................. 36

Table 5.59 rndiff Device Derivation ............................................................................................. 37

Table 5.60 rndiff LVS Checking .................................................................................................. 37

Table 5.61 rpdiff Spice model ..................................................................................................... 37

Table 5.62 rpdiff Device Layers .................................................................................................. 38

Table 5.63 rpdiff Device Derivation ............................................................................................. 38

Table 5.64 rpdiff LVS Checking .................................................................................................. 38

Table 5.65 ccap Spice model ..................................................................................................... 39

Table 5.72 nd LVS Checking ...................................................................................................... 41

Table 5.73 pd Spice model ......................................................................................................... 41

Table 5.74 pd Device Layers ...................................................................................................... 42

Table 5.75 pd Device Derivation ................................................................................................. 42

Table 5.76 pd LVS Checking ...................................................................................................... 42

Table 5.77 spilnd Spice model .................................................................................................... 43

Table 5.78 spiind Device Layers ................................................................................................. 44