QII53018-11.1.0
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Quartus II Handbook Version 11.1
Volume 3: Verification
November 2011
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7. The Quartus II TimeQuest
Timing Analyzer
The Quartus
®
II TimeQuest Timing Analyzer is a powerful ASIC-style timing analysis
tool that validates the timing performance of all logic in your design using an
industry-standard constraint, analysis, and reporting methodology. Use the
TimeQuest analyzer GUI or command-line interface to constrain, analyze, and report
results for all timing paths in your design.
This chapter contains the following sections:
■ “Getting Started with the TimeQuest Analyzer” on page 7–1
■ “Constraining and Analyzing with Tcl Commands” on page 7–7
■ “Creating Clocks and Clock Constraints” on page 7–13
■ “Creating I/O Requirements” on page 7–24
■ “Creating Delay and Skew Constraints” on page 7–26
■ “Creating Timing Exceptions” on page 7–27
■ “Examples of Basic Multicycle Exceptions” on page 7–34
■ “Application of Multicycle Exceptions” on page 7–55
■ “Timing Reports” on page 7–67
f For more information about basic timing analysis concepts and how they pertain to
the TimeQuest analyzer, refer to the Timing Analysis Overview chapter in volume 3 of
the Quartus II Handbook.
f For more information about Altera resources available for the TimeQuest analyzer,
refer to the TimeQuest Timing Analyzer Resource Center of the Altera website.
f For more information about the TimeQuest Timing Analyzer, refer to the Altera
Training page of the Altera website.
Getting Started with the TimeQuest Analyzer
This section provides a brief overview of the design steps necessary to set up your
project for timing and analysis and the steps to perform to constrain your design with
the TimeQuest analyzer.
Running the TimeQuest Analyzer
You can run the TimeQuest analyzer in the following ways:
■ Directly from the Quartus II software GUI
November 2011
QII53018-11.1.0
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