NT51021datasheet_nt51021资源-CSDN文库

5星 · 超过95%的资源需积分: 40 78 浏览量 2018-09-18 16:11:06 上传评论 2 收藏 5.06MB PDF 举报

资源推荐

资源详情

资源评论

NT51021 Spec Note

1803 Channels Source Driver with TCON

MIPI/LVDS Interface

V0.19

Novatek internal use only

NT51021 Spec Note

2014/6/10 3 V0.19

With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a

particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.

List of Content

1. Features.......................................................................................................................................................................... 7

2. General Description ........................................................................................................................................................ 7

3. Function Block Diagram ................................................................................................................................................. 8

4. Application Block Diagram.............................................................................................................................................. 9

5. Pad Sequence (Bump Side) ......................................................................................................................................... 12

6. Pin Descriptions ............................................................................................................................................................ 13

6.1. Value of Wiring Resistance .............................................................................................................................. 21

6.2. The relationship between Pin and Register ..................................................................................................... 22

7. MIPI Interface ............................................................................................................................................................... 24

7.1. Lane Configuration for DSI .............................................................................................................................. 25

7.2. Display Serial Interface (DSI) ........................................................................................................................... 26

8. Command Descriptions ................................................................................................................................................ 31

8.1. MIPI Control Registers ..................................................................................................................................... 31

8.2. Serial Command Interface ............................................................................................................................... 39

8.3. I2C Interface..................................................................................................................................................... 40

8.4. 3-wire and I2C Control Registers ..................................................................................................................... 42

8.5. Control Register Function ................................................................................................................................ 43

9. Function Description ..................................................................................................................................................... 66

9.1. Display Resolutions and Skip Channels .......................................................................................................... 66

9.2. BIST Function .................................................................................................................................................. 66

9.3. VCOM HAOP Application Circuit ..................................................................................................................... 67

9.4. Free Resolution Function ................................................................................................................................. 68

9.5. Trim function .................................................................................................................................................... 70

9.6. GIP control function ......................................................................................................................................... 72

9.7. LVD function..................................................................................................................................................... 72

9.8. SDRRS Function .............................................................................................................................................. 72

9.9. Power On/Off Timing Sequence: ..................................................................................................................... 73

9.10. Input Data VS Output Voltage.......................................................................................................................... 74

9.11. Input Data and Output Voltage Reference Table............................................................................................. 76

9.12. Sun Light readability / CABC / Color Enhancement function ........................................................................... 78

9.13. The Route of Panel and Driving Method .......................................................................................................... 79

10. Data Input Format ......................................................................................................................................................... 82

10.1. Minimum porch timing ...................................................................................................................................... 82

10.2. Data Input format for LVDS .............................................................................................................................. 84

10.3. Data Input Format for MIPI .............................................................................................................................. 87

11. Absolute Maximum Ratings .......................................................................................................................................... 89

12. Recommended Operating Range ................................................................................................................................. 89

13. DC Electrical Characteristics ........................................................................................................................................ 90

13.1. Basic DC Characteristic ................................................................................................................................... 90

13.2. MIPI Interface DC Electrical Characteristic ...................................................................................................... 92

13.3. LVDS Interface DC Electrical Characteristic .................................................................................................... 93

14. AC Electrical Characteristics ........................................................................................................................................ 94

14.1. Basic Input AC Characteristic .......................................................................................................................... 94

14.2. MIPI Interface AC Electrical Characteristic ...................................................................................................... 96

14.3. LVDS Interface AC Electrical Characteristic .................................................................................................. 102

14.4. Output Timing Table ...................................................................................................................................... 104

15. Chip Outline Dimensions ............................................................................................................................................ 107

15.1. Alignment Mark .............................................................................................................................................. 107

15.2. Pad Information .............................................................................................................................................. 107

16. Pad Coordinate ........................................................................................................................................................... 108

17. Appendix A : BIST pattern .......................................................................................................................................... 109

18. Important Notice ......................................................................................................................................................... 110

NT51021 Spec Note

2014/6/10 4 V0.19

With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a

particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.

List of Figures

Figure 1. System Function Block Diagram ...................................................................................................................... 8

Figure 2. Application block diagram for GIP panel .......................................................................................................... 9

Figure 3. Application block diagram with Gate Driver IC............................................................................................... 10

Figure 4. Application block diagram for Landscape panel ............................................................................................ 11

Figure 5. Pad Sequence ................................................................................................................................................ 12

Figure 6. I/O Structure types ......................................................................................................................................... 20

Figure 7. Pin Configuration for DSI ............................................................................................................................... 25

Figure 8. DSI Video Mode Interface Timing Legend ..................................................................................................... 27

Figure 9. Non-Burst Transmission with Sync Start and End ......................................................................................... 28

Figure 10. Non-Burst Transmission with Sync Event ...................................................................................................... 29

Figure 11. Burst Mode Transmission .............................................................................................................................. 30

Figure 12. 3-Wire interface protocol ................................................................................................................................ 39

Figure 13. Definition of I2C-Bus Protocol ........................................................................................................................ 40

Figure 14. I2C bus connection ........................................................................................................................................ 40

Figure 15. Single Register Writing Timing ....................................................................................................................... 41

Figure 16. Single Register Reading Timing .................................................................................................................... 41

Figure 17. I2C bypass mode control ............................................................................................................................... 42

Figure 18. VCOM OP application diagram ...................................................................................................................... 67

Figure 19. HAOP application diagram ............................................................................................................................. 67

Figure 20. Relationship of I2C/OTP/Register .................................................................................................................. 70

Figure 21. Trim operation procedures ............................................................................................................................. 71

Figure 22. LVD function block diagram ........................................................................................................................... 72

Figure 23. SDRRS timing ................................................................................................................................................ 72

Figure 24. Power On Timing Sequence .......................................................................................................................... 73

Figure 25. Power Off Timing Sequence .......................................................................................................................... 73

Figure 26. Power On Black Insertion Sequence ............................................................................................................. 74

Figure 27. Input Data VS Output Voltage ........................................................................................................................ 74

Figure 28. Gamma buffer structure ................................................................................................................................. 75

Figure 29. The route of panel for ZIGZAG=0, ZTYPE=x, ZZ2HB=x ............................................................................... 79

Figure 30. The route of panel for ZIGZAG=1, ZTYPE=1, ZZ2HB=1 ............................................................................... 80

Figure 31. The route of panel for ZIGZAG=1, ZTYPE=1, ZZ2HB=0 ............................................................................... 80

Figure 32. The route of panel for ZIGZAG=1, ZTYPE=0, ZZ2HB=1 ............................................................................... 81

Figure 33. The route of panel for ZIGZAG=1, ZTYPE=0, ZZ2HB=0 ............................................................................... 81

Figure 34. 6-bit LVDS input (LVBIT =L, LVFMT= Don’t Care) ........................................................................................ 84

Figure 35. 8-bit LVDS input (LVBIT =H, LVFMT=L) ........................................................................................................ 84

Figure 36. 8-bit LVDS input (LVBIT =H, LVFMT=H) ....................................................................................................... 84

Figure 37. LVDS input timing format ............................................................................................................................... 85

Figure 38. Data Input Format for MIPI............................................................................................................................. 87

Figure 39. MIPI DC Diagram ........................................................................................................................................... 92

Figure 40. LVDS DC Diagram ......................................................................................................................................... 93

Figure 41. Basic AC timing chart ..................................................................................................................................... 94

Figure 42. 3-wire interface timing .................................................................................................................................... 95

Figure 43. Host I2C interface timing ................................................................................................................................ 95

Figure 44. PMU I2C interface timing ............................................................................................................................... 95

Figure 45. LP Transmitter Timing Definitions .................................................................................................................. 96

Figure 46. Data to Clock Timing Definitions .................................................................................................................... 96

Figure 47. High-Speed Data Transmission in Bursts ...................................................................................................... 97

Figure 48. Switching the Clock Lane between Clock Transmission and Low-Power Mode ........................................... 98

Figure 49. Relationship between VDD, LVDS clock, and internal clock ....................................................................... 102

Figure 50. LVDS cycle time ........................................................................................................................................... 102

Figure 51. LVDS Data Skew ......................................................................................................................................... 103

Figure 52. Frequency Modulation .................................................................................................................................. 103

Figure 53. Vertical Output Timing single STV ............................................................................................................... 104

Figure 54. Vertical Output Timing long STV .................................................................................................................. 104

Figure 55. Gate output timing diagram .......................................................................................................................... 105

NT51021 Spec Note

2014/6/10 5 V0.19

With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a

particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.

Figure 56. Source output timing chart ........................................................................................................................... 105

Figure 57. Source/VCOM/HAOP/Repair OP loading condition ..................................................................................... 106

Figure 58. Chip Outline Dimensions .............................................................................................................................. 107

Figure 59. Alignment Mark ............................................................................................................................................ 107

Figure 60. BIST pattern ................................................................................................................................................. 109

List of Tables

Table 1. Pin Descriptions ............................................................................................................................................. 13

Table 2. TP pin mapping table ..................................................................................................................................... 20

Table 3. Pass Line Description: ................................................................................................................................... 21

Table 4. Wiring Resistance .......................................................................................................................................... 21

Table 5. Pin and Register function mapping ................................................................................................................ 23

Table 6. MIPI Lane Configuration ................................................................................................................................ 24

Table 7. MIPI control registers - Page 0 ...................................................................................................................... 31

Table 8. MIPI control registers - Page 1 ...................................................................................................................... 34

Table 9. MIPI control registers - Page 2 ...................................................................................................................... 35

Table 10. MIPI control registers - Page 3 ...................................................................................................................... 36

Table 11. 3-Wire Command Format ............................................................................................................................... 39

Table 12. 3-Wire Writer Format ...................................................................................................................................... 39

Table 13. 3-Wire Read Format ....................................................................................................................................... 39

Table 14. MIPI / 3-Wire / I2C Register mapping ............................................................................................................ 42

Table 15. GRB: Software Reset ..................................................................................................................................... 43

Table 16. ENTER_SLEEP_MODE: Enter the Sleep-In Mode ....................................................................................... 43

Table 17. EXIT_SLEEP_MODE: Exit the Sleep-In Mode .............................................................................................. 43

Table 18. RDID: Read ID (R80h) ................................................................................................................................... 43

Table 19. PAGE Selection (R83H, R84H)...................................................................................................................... 44

Table 20. Test Mode Control Register(R85H,R86H) ..................................................................................................... 44

Table 21. Command Source Selection(R8FH) .............................................................................................................. 44

Table 22. R89h Control Register .................................................................................................................................... 45

Table 23. R8Bh Control Register ................................................................................................................................... 46

Table 24. R8Ch Control Register ................................................................................................................................... 46

Table 25. R90h Control Register .................................................................................................................................... 47

Table 26. R91h Control Register .................................................................................................................................... 48

Table 27. R92h Control Register .................................................................................................................................... 49

Table 28. R93h Control Register .................................................................................................................................... 50

Table 29. R94h Control Register .................................................................................................................................... 50

Table 30. R95h Control Register .................................................................................................................................... 51

Table 31. R96h Control Register .................................................................................................................................... 51

Table 32. R97h Control Register .................................................................................................................................... 52

Table 33. R98h Control Register .................................................................................................................................... 53

Table 34. R99h Control Register .................................................................................................................................... 53

Table 35. R9Ah Control Register ................................................................................................................................... 54

Table 36. R9Eh Control Register ................................................................................................................................... 55

Table 37. R9Fh Control Register ................................................................................................................................... 55

Table 38. RA4h Control Register ................................................................................................................................... 55

Table 39. RA5h Control Register ................................................................................................................................... 56

Table 40. RA6h Control Register ................................................................................................................................... 56

Table 41. RADh Control Register ................................................................................................................................... 56