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TP2804

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TP2804 2808烧写软件.rar （3个子文件）

TP2804 2808烧写软件

TP2804.pdf 260KB

TP280XISPv5.10.exe 68KB

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TP2804

8051 MICROCONTROLLER WITH 64K FLASH AND ISP

Data Sheet - Version 1.5 Page 1 of 17 http://www.topro.com.tw

November 2005

General Description

The TP2804 is an 8-bit microcontroller which has an

in-system programmable FLASH EPROM for firmware

updated. Its instruction set is fully compatible with

the standard 8051. It contains a 64K-byte FLASH

EPROM, 512-byte on-chip RAM, four 8-bit

bi-directional and bit-addressable I/O ports, an

additional 4-bit I/O port, three 16-bit timer/counters

and one serial port.

Applications

 LCD Monitor

 LCD TV

Features

 Fully static design of 8-bit CMOS microcontroller

 Running clock up to 40MHz

 64K-byte FLASH EPROM

 Low standby current at full supply voltage

 512-byte on-chip RAM (including 256-byte

AUX-RAM, software selectable)

 64K-byte program memory address space and

64K-byte data memory address space

 Four 8-bit bi-directional ports

 One 4-bit multipurpose programmable port

 Three 16-bit timer/counters

 One full duplex serial port

 Eight-source and two-level interrupt capability

 Built-in power management

 Code protection

 Two voltage types: 3.3V and 5V

 Package Forms: DIP40, PLCC44 and PQFP44

Ordering Information

TP2804

Block Diagram

P1.0

P1.7

Port

Port 1

Latch

Interrupt

Timer

UART

Port

P3.0

P3.7

Port 3

Latch

INT2 / INT3

Port 4

Latch

Port

P4.0

P4.3

Oscillator

Bus&Clock

Controller

Instruction

Decoder &

Sequencer

SFR RAM

Address

512 bytes

RAM & SFR

Reset Block Power control

PSW

Stack

Pointer

ALU

T1 T2

A B

P0.0

P0.7

Port

Port 0

Latch

DPTR

Temp Reg.

Intcrementor

64KB

MTP-ROM

Port 2

Latch

P2.0

P2.7

Port

Intcrementor

XTAL1 XTAL2

ALE

PSEN

RST VCC VSS

Voltage

Package Type 2

Package Type 1

Voltage

L: 3.3V

H: 5V

Package Type 1

P: DIP

C: PLCC

Q: PQFP

Package Type 2

G: Green

N: Pb free

TP2804

8051 MICROCONTROLLER WITH 64K FLASH AND ISP

Data Sheet - Version 1.5 Page 2 of 17 http://www.topro.com.tw

November 2005

Pin Configuration

40-PIN DIP

44-PIN PLCC

WR,P3.6

RD,P3.7

XTAL2

XTAL1

VSS

P4.0

A8,P2.0

A9,P2.1

A10,P2.2

A11,P2.3

A12,P2.4

P0.4,AD4

P0.5,AD5

P0.6,AD6

P0.7,AD7

P4.1

ALE

PSEN

P2.7,A15

P2.6,A14

P2.5,A13

P1.5

P1.6

P1.7

RST

RXD,P3.0

INT2,P4.3

TXD,P3.1

INT0,P3.2

INT1,P3.3

T0,P3.4

T1,P3.5

P1.4

P1.3

P1.2

P1.1,T2EX

P1.0,T2

P4.2,INT3

VDD

P0.0,AD0

P0.1,AD1

P0.2,AD2

P0.3,AD3

44-PIN PQFP

P4.1

WR,P3.6

RD,P3.7

XTAL2

XTAL1

VSS

P4.0

A8,P2.0

A9,P2.1

A10,P2.2

A11,P2.3

A12,P2.4

P0.4,AD4

P0.5,AD5

P0.6,AD6

P0.7,AD7

ALE

PSEN

P2.7,A15

P2.6,A14

P2.5,A13

P1.5

P1.6

P1.7

RST

RXD,P3.0

INT2,P4.3

TXD,P3.1

INT0,P3.2

INT1,P3.3

T0,P3.4

T1,P3.5

P1.4

P1.3

P1.2

P1.1

P1.0

P4.2,INT3

VDD

P0.0,AD0

P0.1,AD1

P0.2,AD2

P0.3,AD3

TP2804

8051 MICROCONTROLLER WITH 64K FLASH AND ISP

Data Sheet - Version 1.5 Page 3 of 17 http://www.topro.com.tw

November 2005

Pin Description

Symbol Type Description

EXTERIAL ACCESS ENABLE: This pin should be forced to high level and the program

counter is within the 64 KB area.

PSEN

O/H

PROGRAM STORE ENABLE: When internal ROM access is performed, no

PSEN

strobe signal output is originated from this pin.

ALE O/H

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the

address from the data on Port 0. ALE runs at 1/6

of the oscillator frequency. An ALE

pulse is omitted during external data memory accesses.

RST I/L

RESET: A high on this pin for two machine cycles resets the device while the oscillator is

running.

XTAL1 I

CRYSTAL 1: This is the crystal oscillator input. The pin may be driven by an external

clock.

XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.

I GROUND: Ground potential.

I POWER SUPPLY: Supply voltage for operation.

P0.0 - P0.7 I/O/D PORT 0: Function is the same as that of standard 8051.

P1.0 - P1.7 I/O/H PORT 1: Function is the same as that of standard 8051.

P2.0 - P2.7 I/O/H PORT 2: Function is the same as that of standard 8051.

P3.0 - P3.7 I/O/H PORT 3: Function is the same as that of standard 8051.

P4.0 - P4.3 I/O/H PORT 4: A bi-directional I/O port with internal pull-ups.

NOTES: TYPE I: input; O: output; I/O: bi-directional; H: pull-high; L: pull-low; D: open drain.

Functional Description

The TP2804 architecture consists of a core controller

surrounded by various registers, four general-purpose

I/O port, 512-byte RAM, three timer/counters, a serial

port. Its processor supports 111 different opcodes

and references, both 64K program address space and

64K data storage space.

RAM

The internal data RAM of TP2804 has 512 bytes and

is divided into two banks: scratchpad 256-byte RAM

and 256-byte AUX-RAM. These RAMs are

addressed by different ways:

 RAM 00H-7FH can be addressed directly and

indirectly as the same as in 8051. Address

pointers are R0 and R1 of the selected register

bank.

 RAM 80H-FFH can only be addressed indirectly

as the same as in 8051. Address pointers are

R0 and R1 of the selected registers bank.

 AUX-RAM 00H-FFH is addressed indirectly as

the same way to access external data memory

with the MOVX instruction. Address pointers

are R0 and R1 of the selected register bank and

DPTR register. The AUX-RAM is disabled

after a reset. Setting the bit 4 in CHPCON

AUX-RAM.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data

registers. These are called TL0 and TH0 for Timer 0,

TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer

2. The TCON and TMOD registers provide control

functions for timers 0 and 1. The T2CON register

provides control functions for Timer 2. RCAP2H and

RCAP2L are used as auto-reload or capture registers

for Timer 2 as it in 8051.

The operations of Timer 0 and Timer 1 are the same

as the standard 8051. Timer 2 is a 16-bit

timer/counter that is configured and controlled by the

T2CON register. Like timers 0 and 1, Timer 2 can

operate as either an external event counter or as an

internal timer, depending on the setting of bit C/T2 in

T2CON. Timer 2 has three operating modes:

capture, auto-reload, and baud rate generator. The

clock speed at capture or auto-reload mode is the

same as that of timers 0 and 1.

TP2804

8051 MICROCONTROLLER WITH 64K FLASH AND ISP

Data Sheet - Version 1.5 Page 4 of 17 http://www.topro.com.tw

November 2005

2INT

3INT

Two additional external interrupts,

2INT and

3INT , whose functions are similar to those of

external interrupt 0 and 1 in the XICON (External

Interrupt Control) register. The XICON register is

bit-addressable but is not a standard register in the

standard 8051. Its address is at 0C0H. To set/clear

bits in the XICON register, one can use the “SETB

(

3INT ) bit” instruction.

XICON – external interrupt control

(C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set.

EX3: External interrupt 3 enable if set.

IE3: If IT3 = 1, IE3 is set/cleared automatically by

hardware when interrupt is detected/serviced.

IT3: External interrupt 3 is falling-edge/low-level

triggered when this bit is set/cleared by software.

PX2: External interrupt 2 priority high if set.

EX2: External interrupt 2 enable if set.

IE2: If IT2 = 1, IE2 is set/cleared automatically by

hardware when interrupt is detected/serviced.

IT2: External interrupt 2 is falling-edge/low-level

triggered when this bit is set/cleared by software.

Eight-source Interrupt Information

Interrupt Source

Vector

Address

Polling Sequence

Within Priority Level

Enable Required

Settings

Interrupt Type

Edge/Level

External Interrupt 0 03H 0 (highest) IE.0 TCON.0

Timer/Counter 0 0BH 1 IE.1 -

External Interrupt 1 13H 2 IE.2 TCON.2

Timer/Counter 1 1BH 3 IE.3 -

Serial Port 23H 4 IE.4 -

Timer/Counter 2 2BH 5 IE.5 -

External Interrupt 2 33H 6 XICON.2 XICON.0

External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

Watchdog Timer

The Watchdog timer is a free-running timer that can

be programmed by the user to serve as a system

monitor, a time-base generator or an event timer. It

is basically a set of divider that divides the system

clock and the divider output is selectable and

determines the time-out interval for the time-out

system monitor. This is important in the real-time

control applications. In case of power glitches or

electro-magnetic interference, the processor may

begin to execute errant code. If this is left

unchecked, the entire system may crash. The

watchdog time-out selection will result in different

time-out values depending on the clock speed, and

the watchdog timer will be disabled on reset. In

general, software should restart the watchdog timer to

put it into a known state. The control bits that

support the watchdog timer are discussed as follows:

Watchdog Timer Control Register (8FH)

Bit 7 6 5 4 3 2 1 0

ENW CLRW WIDL - - PS2 PS1 PS0

NOTES:

 ENW: Enable watchdog if set.

 CLRW: Clear watchdog timer and prescaler if set.

This flag will be cleared automatically.

 WIDL: If this bit is set, the watchdog is enabled under

IDLE mode. If cleared, the watchdog is disabled

under IDLE mode. Default is cleared.

 PS2, PS1, PS0: Watchdog prescaler timer select.

Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0 Prescaler Select

0 0 0 2

0 1 0 4

0 0 1 8

0 1 1 16

1 0 0 32

1 0 1 64

1 1 0 128

1 1 1 256

TP2804

8051 MICROCONTROLLER WITH 64K FLASH AND ISP

Data Sheet - Version 1.5 Page 5 of 17 http://www.topro.com.tw

November 2005

Clock

The TP2804 should be used with either a crystal

oscillator or an external clock. Internally, the clock is

divided by twelve before it is used by default. This

makes the TP2804 relatively insensitive to duty cycle

variations in the clock.

Crystal Oscillator

The TP2804 incorporates a built-in crystal oscillator.

To make the oscillator work, a crystal must be

connected across pins XTAL1 and XTAL2. In

addition, a load capacitor must be connected from

each pin to ground, and a resistor must also be

connected from XTAL1 to XTAL2 to provide a DC bias

when the crystal frequency is above 24 MH

External Clock

An external clock should be connected to pin XTAL1.

Pin XTAL2 should be left unconnected. The XTAL1

input is a CMOS-type input as required by the crystal

oscillator. Consequently, the external clock signal

should have an input of one level greater than 3.5

volts.

Power Management

Idle Mode

By setting the IDL bit in the PCON register, the idle

mode is set up. In the idle mode, the internal clock

to the processor is stopped. The peripherals and the

interrupt logic continue to be clocked. The processor

will exit idle mode when either an interrupt or a reset

occurs.

Power-down Mode

When the PD bit in the PCON register is set, the

processor enters the power-down mode. In this

mode, all of the clocks are stopped including the

oscillator. To exit from the power-down mode, it is by

a hardware reset or external interrupts

0INT to

3INT when enabled and set to edge triggered.

Reset

The external RESET signal is sampled at S5P2. To

take effect, it must be held high for at least two

machine cycles while the oscillator is running. An

internal trigger circuit in the reset line is used to

deglitch the reset line when the TP2804 is used with

an external RC network. The reset logic also has a

special glitch removal circuit that ignores glitches on

the reset line. During reset, the ports are initialized

to FFH, the stack pointer to 07H, PCON (with the

exception of bit 4) to 00H, and all of the other SFR

registers except SBUF to 00H. SBUF is not reset.

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