FPGA驱动VGA接口的VHDL语言实现

     
      library IEEE;
      use IEEE.STD_LOGIC_1164.ALL;
      use IEEE.STD_LOGIC_ARITH.ALL;
      use IEEE.STD_LOGIC_UNSIGNED.ALL;
       
      entity vgacore is
          Port ( clk : in std_logic;
             reset : in std_logic;
                 md : in std_logic_vector(1 downto 0);
                 hs : out std_logic;
                 vs : out std_logic;
                 r : out std_logic_vector(1 downto 0);
                 g : out std_logic_vector(2 downto 0);
                 b : out std_logic_vector(2 downto 0)
       );
      end vgacore;
       
      architecture Behavioral of vgacore is
      signal sysclk : std_logic;
      signal hsyncb : std_logic;
      signal vsyncb : std_logic;
      signal enable : std_logic;
      signal hloc : std_logic_vector(9 downto 0);
      signal vloc : std_logic_vector(9 downto 0);
      signal rgbx,rgby,rgbp,rgb: std_logic_vector(7 downto 0);
       
      --定义VGASIG元件，产生同步信号进行行、场扫描，即显示驱动
      component vgasig    
         Port (

             clock : in std_logic;
             reset : in std_logic;
             hsyncb : buffer std_logic;
             vsyncb : out std_logic;
             enable : out std_logic;
             Xaddr : out std_logic_vector(9 downto 0);
             Yaddr : out std_logic_vector(9 downto 0)
        );
      end component;
       
      --定义colormap元件，确定颜色及位置信息
      component colormap 
         Port (
             hloc : in std_logic_vector(9 downto 0);
             vloc : in std_logic_vector(9 downto 0);
             rgbx : out std_logic_vector(7 downto 0);
             rgby : out std_logic_vector(7 downto 0)
        );
      end component;
       
      begin
        rgb(7) <= rgbp(7) and enable;
        rgb(6) <= rgbp(6) and enable;
        rgb(5) <= rgbp(5) and enable;
        rgb(4) <= rgbp(4) and enable;
        rgb(3) <= rgbp(3) and enable;
        rgb(2) <= rgbp(2) and enable;
        rgb(1) <= rgbp(1) and enable;
        rgb(0) <= rgbp(0) and enable;