ETSI
ETSI EN 302 755 V1.1.1 (2009
7.2.3.1 Configurable L1-post signalling ............................................................................................................ 62
7.2.3.2 Dynamic L1-post signalling .................................................................................................................. 66
7.2.3.3 Repetition of L1-post dynamic data ...................................................................................................... 67
7.2.3.4 L1-post extension field .......................................................................................................................... 68
7.2.3.5 CRC for the L1-post signalling ............................................................................................................. 68
7.2.3.6 L1 padding ............................................................................................................................................ 68
7.3 Modulation and error correction coding of the L1 data .................................................................................... 68
7.3.1 Overview .................................................................................................................................................... 68
7.3.1.1 Error correction coding and modulation of the L1-pre signalling ......................................................... 68
7.3.1.2 Error correction coding and modulation of the L1-post signalling ....................................................... 69
7.3.2 FEC Encoding ............................................................................................................................................. 70
7.3.2.1 Zero padding of BCH information bits ................................................................................................. 70
7.3.2.2 BCH encoding ....................................................................................................................................... 72
7.3.2.3 LDPC encoding ..................................................................................................................................... 72
7.3.2.4 Puncturing of LDPC parity bits ............................................................................................................. 72
7.3.2.5 Removal of zero padding bits................................................................................................................ 73
7.3.2.6 Bit interleaving for L1-post signalling .................................................................................................. 74
7.3.3 Mapping bits onto constellations ................................................................................................................ 74
7.3.3.1 Demultiplexing of L1-post signalling ................................................................................................... 74
7.3.3.2 Mapping into I/Q constellations ............................................................................................................ 75
8 Frame Builder ......................................................................................................................................... 75
8.1 Frame structure ................................................................................................................................................. 75
8.2 Super-frame ...................................................................................................................................................... 76
8.3 T2-Frame .......................................................................................................................................................... 77
8.3.1 Duration of the T2-Frame ........................................................................................................................... 77
8.3.2 Capacity and structure of the T2-frame ...................................................................................................... 78
8.3.3 Signalling of the T2-frame structure and PLPs ........................................................................................... 81
8.3.4 Overview of the T2-frame mapping ........................................................................................................... 81
8.3.5 Mapping of L1 signalling information to P2 symbol(s) .............................................................................. 82
8.3.6 Mapping the PLPs ....................................................................................................................................... 84
8.3.6.1 Allocating the cells of the Interleaving Frames to the T2-Frames ........................................................ 84
8.3.6.2 Addressing of OFDM cells for common PLPs and data PLPs .............................................................. 85
8.3.6.3 Mapping the PLPs to the data cell addresses......................................................................................... 86
8.3.6.3.1 Mapping the Common and Type 1 PLPs ......................................................................................... 86
8.3.6.3.2 Mapping the Type 2 PLPs ............................................................................................................... 87
8.3.7 Auxiliary stream insertion .......................................................................................................................... 88
8.3.8 Dummy cell insertion.................................................................................................................................. 89
8.3.9 Insertion of unmodulated cells in the Frame Closing Symbol .................................................................... 89
8.4 Future Extension Frames (FEF) ....................................................................................................................... 89
8.5 Frequency interleaver ....................................................................................................................................... 90
9 OFDM Generation .................................................................................................................................. 94
9.1 MISO Processing .............................................................................................................................................. 95
9.2 Pilot insertion ................................................................................................................................................... 95
9.2.1 Introduction................................................................................................................................................. 95
9.2.2 Definition of the reference sequence .......................................................................................................... 96
9.2.2.1 Symbol level ......................................................................................................................................... 97
9.2.2.2 Frame level ............................................................................................................................................ 97
9.2.3 Scattered pilot insertion .............................................................................................................................. 98
9.2.3.1 Locations of the scattered pilots ............................................................................................................ 98
9.2.3.2 Amplitudes of the scattered pilots ......................................................................................................... 99
9.2.3.3 Modulation of the scattered pilots ....................................................................................................... 100
9.2.4 Continual pilot insertion ........................................................................................................................... 100
9.2.4.1 Locations of the continual pilots ......................................................................................................... 100
9.2.4.2 Locations of additional continual pilots in extended carrier mode ...................................................... 100
9.2.4.3 Amplitudes of the Continual Pilots ..................................................................................................... 100
9.2.4.4 Modulation of the Continual Pilots ..................................................................................................... 101
9.2.5 Edge pilot insertion ................................................................................................................................... 101
9.2.6 P2 pilot insertion ....................................................................................................................................... 101
9.2.6.1 Locations of the P2 pilots .................................................................................................................... 101
9.2.6.2 Amplitudes of the P2 pilots ................................................................................................................. 101
- 1
- 2
前往页