xilinx-04-Implementation_and_STA

This material exempt per Department of Commerce license exception TSU

Zynq

Vivado 2013.4 Version

Implementation and STA

© Copyright 2013 Xilinx

After completing this module, you will be able to:

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Describe setup and hold checks

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Understand the relationship between clocks and setup and hold checks

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Generate a custom timing report to perform basic static timing analysis

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Use the timing summary report to verify your timing constraints were met

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Generate a bitstream and verify the functionality in hardware

Objectives

© Copyright 2013 Xilinx

Implementation

Outline

© Copyright 2013 Xilinx

Implementation: ISE vs. Vivado

© Copyright 2013 Xilinx

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Further logic optimization on fully-assembled netlist

built from synthesized RTL, IP blocks

Optional in non-project batch flow (but

recommended)

opt_design: Logic Optimization

© Copyright 2013 Xilinx