【免费】【STM32实用例程】软件IIC(I2C)+EEPROM(AT24Cxx多型号芯片)通用代码（附带芯片手册）

共80个文件

h：36个

c：35个

work：1个

stm32

IIC协议

EEPROM

AT24C02

AT24C16

需积分: 0 144 浏览量更新于2023-09-15 4 收藏 753KB ZIP 举报

1、【完整例程】基于STM32F103ZET6编写，通过按键控制数据的写入和读取，并通过串口打印读取到的数据； 2、【透彻理解IIC时序】超详细的软件IIC实现代码（带详细注释），初学者可以详细了解IIC协议；重点标注了每个延时函数的作用，便于透彻的理解IIC时序。 3、【一码全包】针对AT24CXX系列芯片编写了通用代码，只需在头文件中更改相关宏定义即可改变芯片型号(支持AT24C01、AT24C02、AT24C04、AT24C08、AT24C16) 4、【单字节读写模式】针对AT24CXX芯片的（RandomRead&BYTEWrite）指定地址的单字节读写模式，编写了相关函数，包括单字节读写、多字节读写、u16和u32型数据的读写函数； 5、【按页连续读写模式】针对AT24CXX芯片的（SequentialRead&PageWrite）指定地址的连续读写模式，编写了以页(Page)为单位的多字节连续读写函数，具体还分为只在当前页操作和可跨页操作两种类型，通过这一部分的学习可深入了解AT24CXX系列芯片的内部存储单元结构和寻址方式，理解“页Page”的概念。

收起资源包目录

IIC+EEPROM.zip （80个子文件）

IIC+EEPROM

keilkilll.bat 399B

User

stm32f10x_conf.h 3KB

stm32f10x.h 619KB

main.c 2KB

stm32f10x_it.c 4KB

stm32f10x_it.h 2KB

Template.uvprojx 18KB

AT24C02.pdf 485KB

Libraries

STM32F10x_StdPeriph_Driver

inc

stm32f10x_bkp.h 7KB

stm32f10x_sdio.h 21KB

stm32f10x_dbgmcu.h 4KB

misc.h 9KB

stm32f10x_cec.h 6KB

stm32f10x_can.h 27KB

stm32f10x_fsmc.h 26KB

stm32f10x_spi.h 17KB

stm32f10x_wwdg.h 3KB

stm32f10x_dma.h 20KB

stm32f10x_exti.h 7KB

stm32f10x_tim.h 51KB

stm32f10x_crc.h 2KB

stm32f10x_rtc.h 4KB

stm32f10x_usart.h 16KB

stm32f10x_rcc.h 30KB

stm32f10x_dac.h 15KB

stm32f10x_adc.h 21KB

stm32f10x_i2c.h 29KB

stm32f10x_gpio.h 20KB

stm32f10x_pwr.h 4KB

stm32f10x_flash.h 25KB

stm32f10x_iwdg.h 4KB

src

stm32f10x_adc.c 46KB

stm32f10x_wwdg.c 6KB

misc.c 7KB

stm32f10x_spi.c 30KB

stm32f10x_gpio.c 23KB

stm32f10x_tim.c 107KB

stm32f10x_sdio.c 28KB

stm32f10x_bkp.c 8KB

stm32f10x_rtc.c 8KB

stm32f10x_dac.c 19KB

stm32f10x_dma.c 29KB

stm32f10x_fsmc.c 35KB

stm32f10x_exti.c 7KB

stm32f10x_pwr.c 9KB

stm32f10x_i2c.c 45KB

stm32f10x_crc.c 3KB

stm32f10x_cec.c 11KB

stm32f10x_can.c 44KB

stm32f10x_iwdg.c 5KB

stm32f10x_usart.c 37KB

stm32f10x_dbgmcu.c 5KB

stm32f10x_flash.c 61KB

stm32f10x_rcc.c 51KB

CMSIS

system_stm32f10x.c 36KB

startup_stm32f10x_hd.s 15KB

core_cm3.h 84KB

core_cm3.c 17KB

system_stm32f10x.h 2KB

Obj

Template.hex 15KB

Public

usart.h 209B

SysTick.h 240B

system.c 525B

system.h 2KB

SysTick.c 1KB

usart.c 3KB

Template.uvguix 94KB

Template.uvoptx 16KB

Template.uvguix.Work 175KB

APP

led

led.h 347B

led.c 967B

iic

iic.h 809B

iic.c 7KB

key

key.c 2KB

key.h 819B

touch_key.h 395B

touch_key.c 6KB

at24cxx

at24cxx.h 2KB

at24cxx.c 12KB

EventRecorderStub.scvd 339B

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Features

• Standard-voltage Operation

– 2.7 (V

= 2.7V to 5.5V)

• Automotive Temperature Range –40°C to 125°C

• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),

1024 x 8 (8K) or 2048 x 8 (16K)

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 400 kHz Compatibility

• Write Protect Pin for Hardware Data Protection

• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

• Partial Page Writes are Allowed

• Self-timed Write Cycle (5 ms max)

• High-reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

• 8-lead JEDEC SOIC and 8-lead TSSOP Packages

Description

The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial

electrically erasable and programmable read-only memory (EEPROM) organized as

128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many

automotive applications where low-power and low-voltage operation are essential.

The AT24C01A/02/04/08A/16A is available in space-saving 8-lead JEDEC SOIC and

8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition,

the entire family is available in 2.7V (2.7V to 5.5V) versions.

Table 1. Pin Configurations

Pin Name Function

A0 − A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

Two-wire

Automotive

Temperature

Serial EEPROM

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

16K (2048 x 8)

AT24C01A

AT24C02

(1)

AT24C04

AT24C08A

AT24C16A

5092C–SEEPR–2/07

Note: 1. AT24C02 not recom-

mended for new

design.

8-lead SOIC

GND

VCC

SCL

SDA

8-lead TSSOP

GND

VCC

SCL

SDA

AT24C01A/02/04/08A/16A

5092C–SEEPR–2/07

Figure 1. Block Diagram

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open-drain or open-

collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device

address inputs that are hard wired for the AT24C01A and the AT24C02. As many as

eight 1K/2K devices may be addressed on a single bus system (device addressing is

discussed in detail under the Device Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K

devices may be addressed on a single bus system. The A0 pin is a no connect.

Absolute Maximum Ratings

Operating Temperature......................................−55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature .........................................−65°C to +150°C

Voltage on Any Pin

with Respect to Ground........................................ −1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

AT24C01A/02/04/08A/16A

5092C–SEEPR–2/07

The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K

devices may be addressed on a single bus system. The A0 and A1 pins are no

connects.

The AT24C16A does not use the device address pins, which limits the number of

devices on a single bus to one. The A0, A1 and A2 pins are no connects.

WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that

provides hardware data protection. The Write Protect pin allows normal read/write oper-

ations when connected to ground (GND). When the Write Protect pin is connected to

, the write protection feature is enabled and operates as shown in the following

table.

Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,

the 1K requires a 7-bit data word address for random word addressing.

AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,

the 2K requires an 8-bit data word address for random word addressing.

AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,

the 4K requires a 9-bit data word address for random word addressing.

AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes

each, the 8K requires a 10-bit data word address for random word addressing.

AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes

each, the 16K requires an 11-bit data word address for random word addressing.

Table 2. Write Protect

WP Pin

Status

Part of the Array Protected

24C01A 24C02 24C04 24C08A 24C16A

At V

Full (1K) Array Full (2K) Array Full (4K) Array Full (8K) Array Full (16K) Array

At GND Normal Read/Write Operations

AT24C01A/02/04/08A/16A

5092C–SEEPR–2/07

Note: 1. This parameter is characterized and is not 100% tested.

Note: 1. V

min and V

max are reference only and are not tested.

Table 3. Pin Capacitance

(1)

Applicable over recommended operating range from T

= 25°C, f = 1.0 MHz, V

= +2.7V

Symbol Test Condition Max Units Conditions

I/O

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

Input Capacitance (A

, A

, SCL) 6 pF V

= 0V

Table 4. DC Characteristics

Applicable over recommended operating range from: T

= −40°C to +125°C, V

= +2.7V to +5.5V (unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Units

CC1

Supply Voltage 2.7 5.5 V

Supply Current V

= 5.0V Read at 100 kHz 0.4 1.0 mA

Supply Current V

= 5.0V Write at 100 kHz 2.0 3.0 mA

SB1

Standby Current V

= 2.7V V

= V

or V

1.6 4.0 µA

SB2

Standby Current V

= 5.0V V

= V

or V

8.0 18.0 µA

Input Leakage Current V

= V

or V

0.10 3.0 µA

Output Leakage Current V

OUT

= V

or V

0.05 3.0 µA

Input Low Level

(1)

−0.6 V

x 0.3 V

Input High Level

(1)

x 0.7 V

+ 0.5 V

OL2

Output Low Level V

= 3.0V I

= 2.1 mA 0.4 V

OL1

Output Low Level V

= 1.8V I

= 0.15 mA 0.2 V

AT24C01A/02/04/08A/16A

5092C–SEEPR–2/07

Note: 1. This parameter is characterized and is not 100% tested (T

= 25°C).

2. This parameter is characterized.

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see to

Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop

condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition

which must precede any other command (see to Figure 5 on page 7).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.

After a read sequence, the stop command will place the EEPROM in a standby power

mode (see Figure 5 on page 7).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from

the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has

received each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode

which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the

completion of any internal operations.

Table 5. AC Characteristics

Applicable over recommended operating range from T

= −40°C to +125°C, V

= +2.7V to +5.5V, CL = 1 TTL Gate and

100 pF (unless otherwise noted)

Symbol Parameter

AT24C01A/02/04/08A/16A

UnitsMin Max

SCL

Clock Frequency, SCL 400 kHz

LOW

Clock Pulse Width Low 1.2 µs

HIGH

Clock Pulse Width High 0.6 µs

Noise Suppression Time

(1)

50 ns

Clock Low to Data Out Valid 0.1 0.9 µs

BUF

Time the bus must be free before

a new transmission can start

(2)

1.2 µs

HD.STA

Start Hold Time 0.6 µs

SU.STA

Start Set-up Time 0.6 µs

HD.DAT

Data In Hold Time 0 µs

SU.DAT

Data In Set-up Time 100 ns

Inputs Rise Time

(2)

300 ns

Inputs Fall Time

(2)

300 ns

SU.STO

Stop Set-up Time 0.6 µs

Data Out Hold Time 50 ns

Write Cycle Time 5 ms

Endurance

(2)

5.0V, 25°C, Page Mode 1M Write Cycles

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