MT2523G/D Reference Manual
Version: 0.4
Release date: 2 September 2016
© 2015 - 2016 MediaTek Inc.
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MT2523G/D Reference Manual
© 2015 -2016 MediaTek Inc.
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This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Document Revision History
Revision Date Description
0.1 2015-12-11 Initial draft
0.2 2016-02-22 Review completed
0.3 2016-06-23 Update G2D, AFE, MMSYS
0.4 2016-09-02 Update MMSYS
Me
dia
Tek
MT2523G/D Reference Manual
© 2015 -2016 MediaTek Inc.
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Table of contents
1. Documentation General Conventions .................................................................................................. 1
1.1. Abbreviations for Control Modules .................................................................................................... 1
1.2. Abbreviations for Registers ................................................................................................................ 2
2. Bus Architecture and Memory Map ..................................................................................................... 3
3. External Interrupt Controller ............................................................................................................... 8
3.1. General Description ............................................................................................................................ 8
3.2. Register Definition ............................................................................................................................ 10
4. Direct Memory Access ....................................................................................................................... 20
4.1. General Description .......................................................................................................................... 20
4.2. Register Definition ............................................................................................................................ 24
5. Universal Asynchronous Receiver Transmitter ................................................................................... 44
5.1. General Description .......................................................................................................................... 44
5.2. Register Definition ............................................................................................................................ 48
6. Serial Peripheral Interface Master Controller ..................................................................................... 63
6.1. General Description .......................................................................................................................... 63
6.2. Register Definition ............................................................................................................................ 66
7. Serial Peripheral Interface Slave Controller ........................................................................................ 73
7.1. General Description .......................................................................................................................... 73
7.2. Register Definition ............................................................................................................................ 77
8. Inter-Integrated Circuit Controller ..................................................................................................... 85
8.1. General Description .......................................................................................................................... 85
8.2. Register Definition ............................................................................................................................ 88
9. SD Memory Card Controller ............................................................................................................... 98
9.1. General Description .......................................................................................................................... 98
9.2. Register Definition .......................................................................................................................... 100
10. USB2.0 High-Speed Device Controller .............................................................................................. 130
10.1. General Description ........................................................................................................................ 130
10.2. Register Definition .......................................................................................................................... 133
11. General Purpose Timer .................................................................................................................... 198
11.1. Introduction .................................................................................................................................... 198
11.2. Register Definition .......................................................................................................................... 200
12. Pulse Width Modulation ................................................................................................................. 221
12.1. General Description ........................................................................................................................ 221
12.2. Register Definition .......................................................................................................................... 222
13. Keypad Scanner .............................................................................................................................. 224
13.1. General Description ........................................................................................................................ 224
13.2. Register Definition .......................................................................................................................... 230
14. General Purpose Counter ................................................................................................................ 234
14.1. General Description ........................................................................................................................ 234
14.2. Register Definition .......................................................................................................................... 235
15. Auxiliary ADC Unit ........................................................................................................................... 239
15.1. General Description ........................................................................................................................ 239
15.2. Register Definition .......................................................................................................................... 240
MT2523G/D Reference Manual
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15.3. Programming Guide ........................................................................................................................ 244
16. General Purpose DAC ...................................................................................................................... 245
16.1. General Description ........................................................................................................................ 245
16.2. Register Definition .......................................................................................................................... 245
16.3. Programming Guide ........................................................................................................................ 247
16.4. Limitations and Important Notes ................................................................................................... 248
17. Accessory Detector ......................................................................................................................... 249
17.1. General Description ........................................................................................................................ 249
17.2. Register Definition .......................................................................................................................... 251
18. True Random Number Generator .................................................................................................... 261
18.1. General Description ........................................................................................................................ 261
18.2. Register Definition .......................................................................................................................... 263
18.3. Programming Guide ........................................................................................................................ 266
19. Audio Front End .............................................................................................................................. 267
19.1. General Description ........................................................................................................................ 267
19.2. Register Definition .......................................................................................................................... 269
20. 2D Acceleration ............................................................................................................................... 291
20.1. General Description ........................................................................................................................ 291
20.2. Features .......................................................................................................................................... 292
20.3. Application Notes ........................................................................................................................... 297
20.4. Register Definitions ........................................................................................................................ 299
21. Multimedia Subsystem Configuration .............................................................................................. 312
21.1. Introduction .................................................................................................................................... 312
21.2. Block diagram ................................................................................................................................. 312
21.3. Register definition .......................................................................................................................... 313
22. LCD display ..................................................................................................................................... 318
22.1. General Description ........................................................................................................................ 318
22.2. LCD registers definition .................................................................................................................. 324
23. Display Serial Interface (DSI) ........................................................................................................... 369
23.1. General Description ........................................................................................................................ 369
23.2. Features .......................................................................................................................................... 369
23.3. Register Definition .......................................................................................................................... 370
24. Image Resizer .................................................................................................................................. 385
24.1. General Description ........................................................................................................................ 385
24.2. Application Notes ........................................................................................................................... 385
24.3. Register Definition .......................................................................................................................... 388
25. Image Rotator DMA ........................................................................................................................ 401
25.1. General Description ........................................................................................................................ 401
25.2. Register Definition .......................................................................................................................... 403
26. General Purpose Inputs/Outputs ..................................................................................................... 411
26.1. General Description ........................................................................................................................ 411
26.2. IO Pull Up/Down Control Truth Table ............................................................................................. 411
26.3. Register Definition .......................................................................................................................... 414
27. MT2523 Top Clock Setting ............................................................................................................... 555
27.1. MT2523 Clock Scheme ................................................................................................................... 555
27.2. Clock Setting Programming Guide .................................................................................................. 556
MT2523G/D Reference Manual
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Lists of tables and figures
Table 2-1. MT2523 bus connection ......................................................................................................................... 3
Table 2-2. Top view memory map .......................................................................................................................... 3
Table 2-3. Always-on domain peripherals............................................................................................................... 4
Table 2-4. Power-down domain peripherals ........................................................................................................... 5
Table 3-1. External interrupt sources ...................................................................................................................... 9
Table 4-1. Virtual FIFO access ports ...................................................................................................................... 23
Table 6-1. SPI master controller interface ............................................................................................................ 64
Table 7-1. SPI slave controller interface ............................................................................................................... 73
Table 7-2. SPI slave command description............................................................................................................ 75
Table 7-3. SPI slave status description (use RS command to poll SPI slave status) .............................................. 75
Table 9-1. Sharing of pins for SD memory card controller .................................................................................... 99
Table 11-1. Operation mode of GPT ................................................................................................................... 198
Table 13-1. 3*3 single key’s order number in COL/ROW matrix ........................................................................ 224
Table 13-2. 3*3 double key’s order number in COL/ROW matrix ...................................................................... 224
Table 15-1. AUXADC channel description ........................................................................................................... 240
Table 20-1. The 2D engine register mapping ...................................................................................................... 299
Table 22-1. LCD controller internal state ............................................................................................................ 320
Table 22-2. LCD TE Ports ..................................................................................................................................... 336
Table 22-3. WROICON.FORMAT List ................................................................................................................... 340
Table 22-4. Layer address alignment constraint ................................................................................................. 353
Table 25-1. ImageRotator DMA Output Format ................................................................................................. 401
Table 25-2. Base Address and Buffer Size Restrictions ....................................................................................... 402
Table 26-1. GPIO v.s. IO type mapping ............................................................................................................... 411
Figure 3-1. Block diagram of external interrupt controller ..................................................................................... 8
Figure 4-1. Variety data paths of DMA transfers .................................................................................................. 20
Figure 4-2. DMA block diagram ............................................................................................................................. 20
Figure 4-3. Ring buffer and double buffer memory data movement ................................................................... 21
Figure 4-4. Unaligned word accesses .................................................................................................................... 22
Figure 4-5. Virtual FIFO DMA ................................................................................................................................ 22
Figure 5-1. Block Diagram of UART ....................................................................................................................... 45
Figure 6-1. Pin connection between SPI master and SPI slave ............................................................................. 63
Figure 6-2. SPI transmission formats .................................................................................................................... 63
Figure 6-3. Operation flow with or without PAUSE mode .................................................................................... 65
Figure 6-4. CS_N de-assert mode .......................................................................................................................... 65
Figure 6-5. Block diagram of SPI master controller ............................................................................................... 65
Figure 7-1. Pin connection between SPI master and SPI slave ............................................................................. 73
Figure 7-2. SPI transmission formats .................................................................................................................... 73
Figure 7-3. SPI slave controller commands waveform .......................................................................................... 74
Figure 7-4. SPI slave control flow diagram ............................................................................................................ 74
