Information Classification: General
Abstract
While maintaining or increasing the number of IO lines over 1024, HBM gen. 4 is
expected to have 12.8-Gb/s pin data rate for further bandwidth improvement. In order to
flatten channel response and alleviate inter-symbol interference (ISI) from on-interposer
channel, HBM gen. 4 requires a new equalizer which satisfies the following
requirements: (1) ISI cancellation effects up to 6.4 GHz or more; (2) low power
consumption; (3) small area consumption.
In this paper, we firstly propose a hybrid equalizer (HE) with an on-interposer
passive equalizer (OIPE) and a 1-tap decision-feedback equalizer (DFE) for HBM gen. 4
I/O. By co-designing an OIPE and a DFE, the proposed HE can overcome the
disadvantage of a 1-tap DFE, long-tail ISI issue, and that of an OIPE, gain drop issue.
Furthermore, it can provide the merits of (1) low power consumption by reducing the
number of taps of DFE and (2) small area consumption by implementing passive
equalizers on the interposer instead of chip. The proposed HE enables 12.8-Gb/s data
transfer of wide I/O lines by successfully opening the closed eye diagram of the 10-mm
long on-interposer channel.
Authors Biography
Yeseul Jeon received the B.S., M.S. and Ph.D. degrees in electrical engineering from the
Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in
2015 and 2021, respectively.
She is now with Massachusetts Institute of Technology (MIT), Cambridge, MA, USA as
a post-doctoral associate. Her research interests include energy-efficient analog and
mixed-signal circuits including wireline and wireless communication ICs and 3-D ICs for
emerging applications such as biomedical devices, wireless sensor nodes and memory
devices. She received IEEE SSCS Rising Star 2020 Award.
Chongsoo Jung received the B.S. and M.S. degrees in electrical engineering from the
Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in
2015 and 2017, respectively. He is currently working toward the Ph.D. degree in the
same school at KAIST.
His research interests include high-speed I/O interfaces, low-power body-channel-
communication (BCC) transceiver design, and low-power clock-generation circuits for
duty-cycled systems.
