iv Intel® PXA27x Processor Family Developer’s Manual
Contents
2.11 Power Management.........................................................................................................2-10
2.12 Signal Descriptions..........................................................................................................2-11
3 Clocks and Power Manager .........................................................................................................3-1
3.1 Overview............................................................................................................................3-1
3.2 Features.............................................................................................................................3-1
3.3 Signal Descriptions............................................................................................................3-2
3.3.1 Hardware Reset (nRESET) ..................................................................................3-3
3.3.2 Internal Reset (nRESET_OUT) ............................................................................3-3
3.3.3 GPIO Wake-Up Sources.......................................................................................3-3
3.3.4 GPIO Reset (nRESET_GPIO/GPIO<1>)..............................................................3-4
3.3.5 Processor Oscillator Input (PXTAL_IN) ................................................................3-4
3.3.6 Processor Oscillator Output (PXTAL_OUT) .........................................................3-4
3.3.7 Processor Clock Input/Output (CLK_PIO/GPIO<9>) ............................................3-4
3.3.8 Timekeeping Oscillator Input (TXTAL_IN)............................................................3-4
3.3.9 Timekeeping Oscillator Output (TXTAL_OUT) .....................................................3-4
3.3.10 Timekeeping Clock Output (CLK_TOUT/GPIO<10>)...........................................3-5
3.3.11 Clock Request (CLK_REQ) ..................................................................................3-5
3.3.12 External Clock (CLK_EXT) ...................................................................................3-5
3.3.13 Battery Fault and VDD Fault (nBATT_FAULT, nVDD_FAULT)............................3-5
3.3.14 Power Enable (PWR_EN).....................................................................................3-5
3.3.15 System Power Enable (SYS_EN).........................................................................3-6
3.3.16 Power Manager I
2
C Clock (PWR_SCL/GPIO<3>) ...............................................3-6
3.3.17 Power Manager I
2
C Data (PWR_SDA/GPIO<4>) ................................................3-6
3.3.18 Power Manager Capacitor Pins (PWR_CAP<3:0>)..............................................3-6
3.3.19 Power Manager Supply Output (PWR_OUT) .......................................................3-6
3.3.20 48-MHz Output Clock (48_MHz)...........................................................................3-6
3.4 Reset Manager Operation .................................................................................................3-6
3.4.1 Reset Types..........................................................................................................3-6
3.4.2 Boot Sequences After Reset ................................................................................3-7
3.4.3 Power-On Reset ...................................................................................................3-7
3.4.4 Hardware Reset....................................................................................................3-8
3.4.5 Watchdog Reset ...................................................................................................3-9
3.4.6 GPIO Reset ........................................................................................................3-10
3.4.7 Summary of Module Reset Sensitivity ................................................................3-12
3.4.8 Summary of Reset Sequences...........................................................................3-12
3.5 Clocks Manager Operation..............................................................................................3-13
3.5.1 External Clock Source Selection (CLK_REQ) ....................................................3-16
3.5.2 13-MHz Processor Oscillator..............................................................................3-17
3.5.3 32.768-kHz Timekeeping Oscillator....................................................................3-18
3.5.4 Peripheral Phase-Locked Loop (312 MHz).........................................................3-19
3.5.5 Core Phase-Locked Loop (Programmable) ........................................................3-19
3.5.6 Functional-Unit Clock Gating..............................................................................3-21
3.5.7 Modifying Clock Frequencies..............................................................................3-21
3.5.8 Summary of Clock Modes...................................................................................3-32
3.6 Power Manager Operation...............................................................................................3-33
3.6.1 Power Domains ..................................................................................................3-36
3.6.2 Internal Voltage Regulators ................................................................................3-36
3.6.3 Power Manager I
2
C Interface .............................................................................3-38
3.6.4 Power Faults and Imprecise-Data Abort.............................................................3-38