//;=======================================================================================================================
//;=======================================================================================================================
//;File: NY8TE64A.h
//;Description: The Header File for NY8TE64A
//;Author: Laurent-Chaung
//;Date: 2021/06/25
//;=======================================================================================================================
//;=======================================================================================================================
//;-----------------------------------------------------------------------------------------------------------------------
//;MOVR and MOVAR instrutions for access R-page Register (General Purpose Register)
//;-----------------------------------------------------------------------------------------------------------------------
//;R-page sregisters ; bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0
//;-----------------------------------------------------------------------------------------------------------------------
//; 0x00 --------- Indirect Addressing Register
//#define INDF 0x00 ; INDF[7] INDF[6] INDF[5] INDF[4] INDF[3] INDF[2] INDF[1] INDF[0]
//; 0x01 --------- Timer0 Data Register
//#define TMR0 0x01 ; TMR0_DATA7 TMR0_DATA6 TMR0_DATA5 TMR0_DATA4 TMR0_DATA3 TMR0_DATA2 TMR0_DATA1 TMR0_DATA0
//; 0x02 --------- Low Byte of Program Counter
//#define PCL 0x02 ; PCL[7] PCL[6] PCL[5] PCL[4] PCL[3] PCL[2] PCL[1] PCL[0]
//; 0x03 --------- Status Register
//#define STATUS 0x03 ; BK[1] BK[0] GP[5] /TO /PD Z DC C
//; 0x04 --------- File Selection Register (Include SRAM Bank Select)
//#define FSR 0x04 ; GP[7] FSR[6] FSR[5] FSR[4] FSR[3] FSR[2] FSR[1] FSR[0]
//; 0x05 --------- PortA Data Register
//#define PORTA 0x05 ; PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0]
//; 0x06 --------- PortB Data Register
//#define PORTB 0x06 ; PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0]
//; 0x07 --------- PortC Data Register
//#define PORTC 0x07 ; - - - - - - PC[1] PC[0]
//; 0x08 --------- Power Control Register (WatchDog, LVD, LVR Control )
//#define PCON 0x08 ; WDTEn /PAPL[4] LVDEn /PHPA[5] LVREn GP[2] EEWR_FAL LOCK
//; 0x09 --------- PortB Wakeup Control Register
//#define BWUCON 0x09 ; WUPB[7] WUPB[6] WUPB[5] WUPB[4] WUPB[3] WUPB[2] WUPB[1] WUPB[0]
//; 0x0A --------- High Byte of Program Counter (B'xxxxxDDD')
//#define PCHBUF 0x0A ; - XSPD_STP - - PCHBUF[3] PCHBUF[2] PCHBUF[1] PCHBUF[0]
//; 0x0B --------- PortA&B Pull-Low Control Register
//#define ABPLCON 0x0B ; /PLPB[3] /PLPB[2] /PLPB[1] /PLPB[0] /PLPA[3] /PLPA[2] /PLPA[1] /PLPA[0]
//; 0x0C --------- PortB Pull-High Control Register
//#define BPHCON 0x0C ; /PHPB[7] /PHPB[6] /PHPB[5] /PHPB[4] /PHPB[3] /PHPB[2] /PHPB[1] /PHPB[0]
//; 0x0D --------- PortC Pull-High Control Register
//#define CPHCON 0x0D ; - - - - - - /PHPC[1] /PHPC[0]
//; 0x0E --------- Interrupt Enable Register
//#define INTE 0x0E ; INT1IE WDTIE - LVDIE T1IE INT0IE PABIE T0IE
//; 0x0F --------- Interrupt Flag Register (Write '0' to Clear Flag)
//#define INTF 0x0F ; INT1IF WDTIF - LVDIF T1IF INT0IF PABIF T0IF
//; 0x10 --------- ADC mode Register
//#define ADMD 0x10 ; ADEn START EOC GCHS CHS[3] CHS[2] CHS[1] CHS[0]
//; 0x11 --------- ADC clock, ADC interrupt flag and ADC low 4-bit data output Register
//#define ADR 0x11 ; ADIF ADIE ADCK[1] ADCK[0] AD[3] AD[2] AD[1] AD[0]
//; 0x12 --------- ADC output data Register (ADC high 8-bit data output Register)
//#define ADD 0x12 ; AD[11] AD[10] AD[9] AD[8] AD[7] AD[6] AD[5] AD[4]
//; 0x13 --------- ADC high reference voltage Register
//#define ADVREFH 0x13 ; EVHEnB - - - - - VHS[1] VHS[0]
//; 0x14 --------- ADC Sampling pulse width and ADC conversion bit Register and AIN pin control Register
//#define ADCR 0x14 ; PBCON[7] PBCON[6] PBCON[5] PBCON[4] SHCK[1] SHCK[0] ADCR[1] ADCR[0]
//; 0x15 --------- PortA Wakeup Control Register
//#define AWUCON 0x15 ; WUPA[7] WUPA[6] WUPA[5] WUPA[4] WUPA[3] WUPA[2] WUPA[1] WUPA[0]
//; 0x16 --------- AIN pin control Register
//#define PACON 0x16 ; PBCON[3] PBCON[2] PBCON[1] PACON[4] PACON[3] PACON[2] PACON[1] PACON[0]
//; 0x17 --------- ADOFFSET
//#define ADJMD 0x17 ; - - ADJ_SIGN ADJ[4] ADJ[3] ADJ[2] ADJ[1] ADJ[0]
//; 0x18 --------- External Interrupt Contorl Register
//#define INTEDG 0x18 ; INT2DEG ExINT2En ExINT1En ExINTEn INT1_Edg[1] INT1_Edg[0] INT_Edg[1] INT_Edg[0]
//; 0x19 --------- TIMER1 Data and PWMDUTY1 msb 2 bits Register
//#define TMRH 0x19 ; - - TMR1_DATA9 TMR1_DATA8 PWM2_DUTY9 PWM2_DUTY8 PWM1_DUTY9 PWM1_DUTY8
//; 0x1A --------- Analog Circuit Enable Register
//#define ANAEN 0x1A ; CMPEn - - - - - - -
//; 0x1B --------- Resistor to Frequency Converter Control Register
//#define RFC 0x1B ; RFCEn - - - PADSel[3] PADSel[2] PADSel[1] PADSel[0]
//; 0x1C --------- TIMER3 Data and PWMDUTY3 msb 2 bits Register
//#define TMR4RH 0x1C ; TMR4_DATA9 TMR4_DATA8 - - PWM4_DUTY9 PWM4_DUTY8 PWM3_DUTY9 PWM3_DUTY8
//; 0x1D --------- I_HRC frequency Trim High Byte
//#define OSCCALH 0x1D ; - - - - - OSC[10] OSC[9] OSC[8]
//; 0x1E --------- I_HRC frequency Trim Low Byte
//#define OSCCALL 0x1E ; OSC[7] OSC[6] OSC[5] OSC[4] OSC[3] OSC[2] OSC[1] OSC[0]
//; 0x1F --------- Interrupt2 Enable/Flag Register
//#define INTE2 0x1F ; INT2IF T4IF - - INT2IE T4IE - -
//;-----------------------------------------------------------------------------------------------------------------------
//;T0MD and T0MDR instrutions for access T0MD Register
//;-----------------------------------------------------------------------------------------------------------------------
//; 0xx --------- Timer0 Control Register (Only Accessed by Instruction T0MD)
//;T0MD 0x0xx ; LClkSrc GP[6] ClkSel EdgeSel PS0WDT PS0Div[2] PS0Div[1] PS0Div[0]
//;-----------------------------------------------------------------------------------------------------------------------
//;IOST and IOSTR instrution for access F-page Register (IO Configuration Register)
//;-----------------------------------------------------------------------------------------------------------------------
//;F-page registers ; bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0
//;-----------------------------------------------------------------------------------------------------------------------
//; 0x01 --------- Reserved
//; 0x02 --------- Reserved
//; 0x03 --------- Reserved
//; 0x04 --------- Reserved
//; 0x05 --------- PortA Direction(1:Input/0:Output) Control Register
//#define IOSTA 0x05 ; IOPA[7] IOPA[6] IOPA[5] IOPA[4] IOPA[3] IOPA[2] IOPA[1] IOPA[0]
//; 0x06 --------- PortB Direction(1:Input/0:Output) Control Register
//#define IOSTB 0x06 ; IOPB[7] IOPB[6] IOPB[5] IOPB[4] IOPB[3] IOPB[2] IOPB[1] IOPB[0]
//; 0x07 --------- PortC Direction(1:Input/0:Output) Control Register
//#define IOSTC 0x07 ; - - - - - - IOPC[1] IOPC[0]
//; 0x08 --------- Reserved
//; 0x09 --------- PortA Pull-High Control Register (/PA[5]: Pull-Low)
//#define APHCON 0X09 ; /PHPA[7] /PHPA[6] /PLPA[5] /PHPA[4] /PHPA[3] /PHPA[2] /PHPA[1] /PHPA[0]
//; 0x0A --------- Prescaler0 Counter Value Register
//#define PS0CV 0x0A ; PS0CV[7] PS0CV[6] PS0CV[5] PS0CV[4] PS0CV[3] PS0CV[2] PS0CV[1] PS0CV[0]
//; 0x0B --------- PortC Pull-Low Control Register
//#define CPLCON 0X0B ; - - - - - - /PLPC[1] /PLPC[0]
//; 0x0C --------- PortB Open-Drain Control Register
//#define BODCON 0x0C ; /ODPB[7] /ODPB[6] /ODPB[5] /ODPB[4] /ODPB[3] /ODPB[2] /ODPB[1] /ODPB[0
九齐例程NY8-Example V1.4， （4939个子文件） 
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