基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文_(2).docx

外文文献原稿和译文

原稿

The Description of AT89S51

1 General Description

The AT89S51 is a low-power, high-performance CMOS 8-bit

microcontroller with 4K bytes of In-System Programmable Flash memory.

The device is manufactured using Atmel’s high-density nonvolatile

cost-effective solution to many embedded control applications.

The AT89S51 provides the following standard features: 4K bytes of

Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data

pointers, two 16-bit timer/counters, a five-vector two-level

interrupt architecture, a full duplex serial port, on-chip oscillator,

and clock circuitry. In addition, the AT89S51 is designed with static

logic for operation down to zero frequency and supports two software

selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM,

timer/counters, serial port, and interrupt system to continue

to port 0 pins, the pins can be used as high-impedance inputs. Port 0

can also be configured to be the multiplexed low-order address/data

bus during accesses to external program and data memory. In this mode,

P0 has internal pull-ups. Port 0 also receives the code bytes during

Flash programming and outputs the code bytes during program

verification. External pull-ups are required during program

verification.

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups.

The Port 1 output buffers can sink/source four TTL inputs. When 1s

are written to Port 1 pins, they are pulled high by the internal

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups.

The Port 2 output buffers can sink/source four TTL inputs. When 1s

are written to Port 2 pins, they are pulled high by the internal

pull-ups and can be used as inputs. As inputs, Port 2 pins that are

externally being pulled low will source current (I

IL

) because of the

internal pull-ups.Port 2 emits the high-order address byte during

fetches from external program memory and during accesses to external

data memory that use 16-bit addresses (MOVX DPTR). In this

application, Port 2 uses strong internal pull-ups when emitting 1s.

Register. Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups.

The Port 3 output buffers can sink/source four TTL inputs. When 1s

are written to Port 3 pins, they are pulled high by the internal

pull-ups and can be used as inputs. As inputs, Port 3 pins that are

externally being pulled low will source current (I

IL

) because of the

pull-ups. Port 3 receives some control signals for Flash programming

and verification. Port 3 also serves the functions of various special

features of the AT89S51, as shown in the following table.

3 Special Function Registers

A map of the on-chip memory area called the Special Function

Register (SFR) space is shown in Table 3-1.

Table 3-1. AT89S51 SFR Map and Reset Values

Note that not all of the addresses are occupied, and unoccupied

addresses may not be implemented on the chip. Read accesses to these

addresses will in general return random data, and write accesses will

have an indeterminate effect.

Table 3-2. AUXR:Auxiliary Register