EEPROMXILINX_jtag-hs2资源-CSDN文库

共46个文件

prj：7个

v：4个

html：4个

EEPROM

XIlinx

需积分: 9 142 浏览量 2012-07-02 16:40:09 上传评论 1 收藏 124KB ZIP 举报

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EEPROM.zip （46个子文件）

EEPROM

fuse.xmsgs 604B

EEPROM_WR.v 10KB

Top.prj 22B

Signal_beh.prj 0B

xilinxsim.ini 0B

ipcore_dir

Top_beh.prj 84B

Signal.stx 1KB

EEPROM.xst 1KB

iseconfig

EEPROM.projectmgr 8KB

Top.xreport 20KB

EEPROM.xreport 20KB

fuseRelaunch.cmd 158B

EEPROM_envsettings.html 9KB

.lso 22B

EEPROM.xise 36KB

Top.xst 1KB

singal.bmm 0B

Top.cmd_log 1KB

Signal_stx_beh.prj 0B

Signal.spl 116B

Top_stx_beh.prj 94B

Top.syr 5KB

Signal.tfi 190B

_xmsgs

pn_parser.xmsgs 2KB

xst.xmsgs 745B

EEPROM.syr 4KB

fuse.log 504B

Top_envsettings.html 9KB

Top.lso 6B

EEPROM.v 3KB

Signal.cmd_log 467B

EEPROM_ise12migration.zip 80KB

Signal.prj 0B

EEPROM.lso 6B

EEPROM_summary.html 4KB

EEPROM.gise 1KB

Top_summary.html 4KB

Top.v 478B

EEPROM.cmd_log 2KB

EEPROM.prj 25B

Top_xst.xrpt 9KB

webtalk_pn.xml 3KB

Signal.xst 144B

signal.v 2KB

Signal.sym 2KB

EEPROM_xst.xrpt 9KB

<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <center><big><big>System Settings</big></big></center> <A NAME="Environment Settings"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='5'> Environment Settings </TD> </tr> <tr bgcolor='#ffff99'> <td>Environment Variable</td> <td>xst</td> <td>ngdbuild</td> <td>map</td> <td>par</td> </tr> <tr> <td>PATHEXT</td> <td>.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>Path</td> <td>d:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64; d:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64; D:\Xilinx\13.3\ISE_DS\PlanAhead\bin; D:\Xilinx\13.3\ISE_DS\ISE\bin\nt64; D:\Xilinx\13.3\ISE_DS\ISE\lib\nt64; D:\Xilinx\13.3\ISE_DS\EDK\bin\nt64; D:\Xilinx\13.3\ISE_DS\EDK\lib\nt64; D:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin; D:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; D:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin; D:\Xilinx\13.3\ISE_DS\common\bin\nt64; D:\Xilinx\13.3\ISE_DS\common\lib\nt64; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; e:\Program Files\MATLAB\R2010b\runtime\win64; e:\Program Files\MATLAB\R2010b\bin; C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\; C:\Program Files\Microsoft SQL Server\100\Tools\Binn\; C:\Program Files\Microsoft SQL Server\100\DTS\Binn\; C:\Program Files (x86)\Common Files\Thunder Network\KanKan\Codecs; D:\Xilinx\ModelSim6_5\win32; D:\modeltech_6.5e\win32</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX</td> <td>d:\Xilinx\13.3\ISE_DS\ISE\</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_DSP</td> <td>D:\Xilinx\13.3\ISE_DS\ISE</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_EDK</td> <td>D:\Xilinx\13.3\ISE_DS\EDK</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_PLANAHEAD</td> <td>D:\Xilinx\13.3\ISE_DS\PlanAhead</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> </TABLE> <A NAME="Synthesis Property Settings"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='4'>Synthesis Property Settings </TD> </tr> <tr bgcolor='#ffff99'> <td>Switch Name</td> <td>Property Name</td> <td>Value</td> <td>Default Value</td> </tr> <tr> <td>-ifn</td> <td> </td> <td>EEPROM.prj</td> <td> </td> </tr> <tr> <td>-ifmt</td> <td> </td> <td>mixed</td> <td>MIXED</td> </tr> <tr> <td>-ofn</td> <td> </td> <td>EEPROM</td> <td> </td> </tr> <tr> <td>-ofmt</td> <td> </td> <td>NGC</td> <td>NGC</td> </tr> <tr> <td>-p</td> <td> </td> <td>xc5vlx110t-2-ff1136</td> <td> </td> </tr> <tr> <td>-top</td> <td> </td> <td>EEPROM</td> <td> </td> </tr> <tr> <td>-opt_mode</td> <td>Optimization Goal</td> <td>Speed</td> <td>SPEED</td> </tr> <tr> <td>-opt_level</td> <td>Optimization Effort</td> <td>1</td> <td>1</td> </tr> <tr> <td>-power</td> <td>Power Reduction</td> <td>NO</td> <td>NO</td> </tr> <tr> <td>-iuc</td> <td>Use synthesis Constraints File</td> <td>NO</td> <td>NO</td> </tr> <tr> <td>-keep_hierarchy</td> <td>Keep Hierarchy</td> <td>No</td> <td>NO</td> </tr> <tr> <td>-netlist_hierarchy</td> <td>Netlist Hierarchy</td> <td>As_Optimized</td> <td>as_optimized</td> </tr> <tr> <td>-rtlview</td> <td>Generate RTL Schematic</td> <td>Yes</td> <td>NO</td> </tr> <tr> <td>-glob_opt</td> <td>Global Optimization Goal</td> <td>AllClockNets</td> <td>ALLCLOCKNETS</td> </tr> <tr> <td>-read_cores</td> <td>Read Cores</td> <td>YES</td> <td>YES</td> </tr> <tr> <td>-write_timing_constraints</td> <td>Write Timing Constraints</td> <td>NO</td> <td>NO</td> </tr> <tr> <td>-cross_clock_analysis</td> <td>Cross Clock Analysis</td> <td>NO</td> <td>NO</td> </tr> <tr> <td>-bus_delimiter</td> <td>Bus Delimiter</td> <td><></td> <td><></td> </tr> <tr> <td>-slice_utilization_ratio</td> <td>Slice Utilization Ratio</td> <td>100</td> <td>100%</td> </tr> <tr> <td>-bram_utilization_ratio</td> <td>BRAM Utilization Ratio</td> <td>100</td> <td>100%</td> </tr> <tr> <td>-dsp_utilization_ratio</td> <td>DSP Utilization Ratio</td> <td>100</td> <td>100%</td> </tr> <tr> <td>-reduce_control_sets</td> <td> </td> <td>Off</td> <td>OFF</td> </tr> <tr> <td>-verilog2001</td> <td>Verilog 2001</td> <td>YES</td> <td>YES</td> </tr> <tr> <td>-fsm_extract</td> <td> </td> <td>YES</td> <td>YES</td> </tr> <tr> <td>-fsm_encoding</td> <td> </td> <td>Auto</td> <td>AUTO</td> </tr> <tr> <td>-safe_implementation</td> <td> </td> <td>No</td> <td>NO</td> </tr> <tr> <td>-fsm_style</td> <td> </td> <td>LUT</td> <td>LUT</td> </tr> <tr> <td>-ram_extract</td> <td> </td> <td>Yes</td> <td>YES</td> </tr> <tr> <td>-ram_style</td> <td> </td> <td>Auto</td> <td>AUTO</td> </tr> <tr> <td>-rom_extract</td> <td> </td> <td>Yes</td> <td>YES</td> </tr> <tr> <td>-shreg_extract</td> <td> </td> <td>YES</td> <td>YES</td> </tr> <tr> <td>-rom_style</td> <td> </td> <td>Auto</td> <td>AUTO</td> </tr> <tr> <td>-auto_bram_packing</td> <td> </td> <td>NO</td> <td>NO</td> </tr> <tr> <td>-resource_sharing</td> <td> </td> <td>YES</td> <td>YES</td> </tr> <tr> <td>-async_to_sync</td> <td> </td> <td>NO</td> <td>NO</td> </tr> <tr> <td>-use_dsp48</td> <td> </td> <td>Auto</td> <td>AUTO</td> </tr> <tr> <td>-iobuf</td> <td> </td> <td>YES</td> <td>YES</td> </tr> <tr> <td>-max_fanout</td> <td> </td> <td>100000</td> <td>100000</td> </tr> <tr> <td>-bufg</td> <td> </td> <td>32</td> <td>32</td> </tr> <tr> <td>-register_duplication</td> <td> </td> <td>YES</td> <td>YES</td> </tr> <tr> <td>-register_balancing</td> <td> </td> <td>No</td> <td>NO</td> </tr> <tr> <td>-optimize_primitives</td> <td> </td> <td>NO</td> <td>NO</td> </tr> <tr> <td>-use_clock_enable</td> <td> </td> <td>Auto</td> <td>AUTO</td> </tr> <tr> <td>-use_sync_set</td> <td> </td> <td>Auto</td> <td>AUTO</td> </tr> <tr> <td>-use_sync_reset</td> <td> </td> <td>Auto</td> <td>AUTO</td> </tr> <tr> <td>-iob</td> <td> </td> <td>Auto</td> <td>AUTO</td> </tr> <tr> <td>-equivalent_register_removal</td> <td> </td> <td>YES</td> <td>YES</td> </tr> <tr> <td>-slice_utilization_ratio_maxmargin</td> <td> </td> <td>5</td> <td>0%</td> </tr> </TABLE> <A NAME="Operating System Information"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='5'> Operating System Information </TD> </tr> <tr bgcolor='#ffff99'> <td>Operating System Inf

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