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MAX96712 数据表 MAX96712 是一款高性能的Deserializer，能够将 GMSL2 或 GMSL1 序列输入转换为 MIPI CSI-2 D-PHY 或 C-PHY 格式的输出。该设备允许多达四个远程位于传感器使用工业标准同轴或 STP 连接器。每个 GMSL2 序列链路在正向方向以 3Gbps 或 6Gbps 固定速率传输，并在反向方向以 187.5Mbps 传输。在 GMSL1 模式下，MAX96712 可与第一代 3.12Gbps 或 1.5Gbps GMSL1 序列器配对，或者在 GMSL1 模式下以 3.12Gbps 速率传输与 GMSL2 序列器配合使用。 MAX96712 支持聚合和复制视频数据，允许多个远程位于传感器的流媒体被组合并路由到一个或多个可用的 CSI-2 输出中。数据也可以根据虚拟频道 ID 进行路由，允许多个流媒体从单个 GMSL 输入被独立路由到不同的 CSI-2 输出。此外，来自多个传感器的数据也可以在单个 CSI-2 流媒体中被同步和组合使用帧 concatenate。 CSI-2 接口支持 2x 4-lane 和 4x 2-lane 配置，使用 C-PHY 或 D-PHY。该设备还提供了多种外围通信选项，以实现灵活的本地寄存器访问和远程设备编程。三个 I2C/UART 端口支持冗余的本地和远程内部寄存器访问，包括并发或隧道式远程外围通信。此外，还提供了两个 SPI 端口，作为隧道式接口连接到远程外围设备（GMSL2）。 MAX96712 的操作温度范围为 -40°C 到 +105°C，符合汽车温度范围的要求，并且该设备获得了 AEC-Q100 认证。该设备适用于高分辨率摄像系统、后视摄像机、驾驶员监控系统、姿势摄像机、高安全性 ADAS/自动驾驶传感器、雷达、激光雷达和周围视觉系统等应用场景。知识点： 1. MAX96712 是一款Deserializer，能够将 GMSL2 或 GMSL1 序列输入转换为 MIPI CSI-2 D-PHY 或 C-PHY 格式的输出。 2. 该设备支持聚合和复制视频数据，允许多个远程位于传感器的流媒体被组合并路由到一个或多个可用的 CSI-2 输出中。 3. MAX96712 支持 GMSL2 和 GMSL1 两种模式，能够与第一代 3.12Gbps 或 1.5Gbps GMSL1 序列器配对，或者在 GMSL1 模式下以 3.12Gbps 速率传输与 GMSL2 序列器配合使用。 4. 该设备提供了多种外围通信选项，包括三个 I2C/UART 端口和两个 SPI 端口，支持冗余的本地和远程内部寄存器访问。 5. MAX96712 的操作温度范围为 -40°C 到 +105°C，符合汽车温度范围的要求，并且该设备获得了 AEC-Q100 认证。 6. 该设备适用于高分辨率摄像系统、后视摄像机、驾驶员监控系统、姿势摄像机、高安全性 ADAS/自动驾驶传感器、雷达、激光雷达和周围视觉系统等应用场景。

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General Description

The MAX96712 deserializer converts GMSL2 or GMSL1

serial inputs into MIPI CSI-2 D-PHY or C-PHY formatted

outputs. The device allows each link to simultaneously

transmit bidirectional control-channel data while forward

video transmissions are in progress. The MAX96712 can

accommodate as many as four remotely located sensors

using industry-standard coax or STP interconnects. Each

GMSL2 serial link operates at a fixed rate of 3Gbps or

6Gbps in the forward direction and 187.5Mbps in the

reverse direction. In GMSL1 mode, the MAX96712 can be

paired with first-generation 3.12Gbps or 1.5Gbps GMSL1

serializers or operate up to 3.12Gbps with GMSL2 serial-

izers in GMSL1 mode.

The MAX96712 supports both aggregation and replication

of video data, enabling streams from multiple remotely

located sensors to be combined and routed to one or more

of the available CSI-2 outputs. Data can also be routed

based on virtual channel ID, enabling multiple streams

from a single GMSL input to be routed independently to

different CSI-2 outputs. Alternatively, data from multiple

sensors can be synchronized and combined in a single

CSI-2 stream within a composite superframe using frame

concatenation. The CSI-2 interface supports both 2x 4-lane

and 4x 2-lane configurations using either C-PHY or D-PHY.

A variety of peripheral communication options are pro-

vided for flexible local register access and remote device

programming. Three I

C/UART ports support redundant

local and remote internal register access with concurrent

or tunneled remote peripheral communication. An addi-

tional two SPI ports are provided as tunneling interfaces

to remote peripherals (GMSL2).

Operation is specified over the automotive temperature

range of -40°C to +105°C with proper thermal design, and

the device is AEC-Q100 qualified.

Applications

● High-Resolution Camera Systems

• Rear-View Cameras

• Driver Monitoring Systems

• Gesture Cameras

● Safety Critical ADAS/Autonomous Driving Sensors

• RADAR

• LIDAR

• Surround-View Cameras

• High-Resolution Cameras

● Synchronized Multisensor Systems

Ordering Information appears at end of data sheet.

19-100544; Rev 0; 5/19

Benets and Features

● MIPI CSI-2 v1.3 Output Configurable as 2x4 Lane,

1x4 Lane + 2x2 Lane, or 4x2 Lane

• Selectable D-PHY v1.2 at 80Mbps to 2.5Gbps/

Lane or C-PHY v1.0 at 182Mbps to 5.7Gbps/Lane

• 16/32-Channel Virtual Channel Support (D/C-PHY)

• Flexible Aggregation and Routing of Incoming Data

via CSI-2 VC or Frame Concatenation

• Data can be Replicated and Routed to any CSI Port

• Supports RAW8/10/12/14/16/20,

RGB565/666/888,YUV422 8/10-Bit Formats

• Double Pixel Mode for Transmission E󰀩ciency

• CSI-2 Lane Reassignment and Polarity Flip

• MIPI/GMSL Video PRBS Generator and Checker

• Checkerboard/Color Gradient Pattern Generator

• Raw CSI-2 PRBS Generator

• Independent Conguration of all Video Paths and

GMSL/CSI-2 Ports

● Quad GMSL Inputs with Independently Configurable

GMSL1/2 Operation, Link Speed, and Video Format

• Mixed GMSL1/GMSL2 and 3G/6G Support

• Backward compatible with GMSL1 Serializers

• GMSL1 Forward Link Speed up to 3.12Gbps

• GMSL2 Link Speed of 3Gbps or 6Gbps (Forward)

and 187.5Mbps (Reverse)

• Simultaneous Support of Both Synchronized and

Non-Synchronized Cameras

• Enables Precise Synchronization of Multiple Serial-

izers for Large Camera Systems

• GMSL PRBS Generator/Checker for Link Testing

• Eye-Opening Monitor for Continuous Diagnostics

• Adaptive Equalization Enables up to 15m Coax

Cable with Multiple In-Line Connectors

• Compatible with 50Ω Coax or 100Ω STP

● ASIL-B Compliant (GMSL2)

• Video Watermark Insertion and Detection

• 16-Bit CRC Protection of Control-Channel Data

with Retransmission Upon Error Detection

• Optional 32-Bit CRC Protection of Video Line Data

• ECC Protection of Video Data Memory

• CRC Protection of CSI-2 Data Streams

● Concurrent Control Channel for Device Configuration

and Communicating with Remote Peripherals

• 3x I

C/UART, 2x SPI, 17x GPIO

• Eight Hardware-Selectable Device Addresses

● Programmable Spread Spectrum for EMI Reduction

● 64-lead 9mm x 9mm TQFN with Exposed Pad

Click here for production status of specic part numbers.

MAX96712 Quad GMSL2 to CSI-2 Deserializer

with GMSL1 Compatibility

General Description ............................................................................ 1

Applications

.................................................................................. 1

Benefits and Features

.......................................................................... 1

Simplified Block Diagram

........................................................................ 6

Absolute Maximum Ratings

...................................................................... 7

Package Information

........................................................................... 7

64-pin TQFN

................................................................................7

64-pin TQFN-SW (Side-Wettable)

...............................................................7

DC Electrical Characteristics

..................................................................... 8

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Typical Operating Characteristics

................................................................ 20

Pin Configuration

............................................................................. 22

Pin Description

............................................................................... 23

Functional Diagrams

.......................................................................... 33

Recommended Operating Conditions

............................................................. 34

External Component Requirements

.............................................................34

Functional Diagrams

.......................................................................... 36

Detailed Description

........................................................................... 46

Introduction

................................................................................46

Product Overview

...........................................................................46

GMSL2 Overview

...........................................................................50

Video Pipeline

...........................................................................51

Video Pipes, Aggregation, and Replication

.....................................................51

Video Crossbar

..........................................................................56

Watermarking

............................................................................56

Video Line CRC

..........................................................................56

Video Timing Monitor

......................................................................56

Video Memory ECC Protection

..............................................................56

Control Channel and Side Channels

..........................................................56

C/UART ...............................................................................57

SPI

....................................................................................58

Control Channel Latency

...................................................................59

General Purpose Inputs and Outputs (GPIO)

...................................................59

GMSL2 Physical Layer

....................................................................60

Cabling Options

..........................................................................60

GMSL2 Bandwidth Sharing

.................................................................60

GMSL2 Bandwidth Calculations

.............................................................60

TABLE OF CONTENTS

www.maximintegrated.com

Maxim Integrated

│

MAX96712 Quad GMSL2 to CSI-2 Deserializer

with GMSL1 Compatibility

Eye-Opening Monitor......................................................................61

Video PRBS Generator/Checker

.............................................................61

Link Error Generator

......................................................................61

AEQ (Adaptive Equalization)

................................................................61

GMSL1 Backwards Compatibility

...............................................................62

CSI Video Output Ports

......................................................................62

MIPI Transmit Clock Spreading

..............................................................62

Video Pattern Generator

...................................................................62

Video PRBS Generator/Checker

.............................................................64

CSI Output Raw PRBS Generator

............................................................64

CFG Latch at Power-up Pins

..................................................................64

Multifunction Pin Configuration

.................................................................65

Speed Programming for SPI

................................................................67

Power-up and Link Start-up

...................................................................68

Device Reset

............................................................................68

Link and Video Lock

.........................................................................68

Link Lock

...............................................................................68

Video Lock

..............................................................................68

Clocking

..................................................................................68

Reference Clock

.........................................................................68

Spread-Spectrum Clocking

.................................................................69

Error and Fault Condition Monitoring

............................................................69

Power Supplies

.............................................................................69

Power Supply Monitoring

...................................................................69

Standby and Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Thermal Management

........................................................................70

Applications Information

........................................................................ 70

Control Channel Programming

.................................................................70

Host-to-Peripheral Main I

C and Pass-Through I

C Communication.................................70

C Write Packet Format ...................................................................70

C Read Packet Format ...................................................................70

Device Address

..........................................................................71

Main I

C Host-to-GMSL2 Device Communication ...............................................71

Main UART

..............................................................................71

UART Base Mode

........................................................................71

UART Bypass Mode

......................................................................71

Switching Between UART Base and Bypass Modes

.............................................71

TABLE OF CONTENTS

(

CONTINUED

)

www.maximintegrated.com

Maxim Integrated

│

MAX96712 Quad GMSL2 to CSI-2 Deserializer

with GMSL1 Compatibility

UART Frame Format ......................................................................72

Synchronization Frame

....................................................................72

Acknowledge Frame

......................................................................72

Write Packet

.............................................................................73

Read Packet

.............................................................................73

Ordering Information

.......................................................................... 73

Revision History

...............................................................................74

Figure 1. GMSL2 Serial Output Parameters

........................................................ 36

Figure 2. GMSL1 Serial Output Parameters

........................................................ 36

Figure 3. D-PHY DC Characteristics

.............................................................. 37

Figure 4. D-PHY Possible ∆V

CMTX

and ∆V

Distortions of Single-ended HS Signals ...................... 37

Figure 5. D-PHY Ideal Single-ended and Resulting Differential HS Signals

............................... 38

Figure 6. C-PHY DC Characteristics

.............................................................. 38

Figure 7. C-PHY Possible ∆V

CPTX

and ∆V

Distortions of Single-Ended HS Signals ...................... 39

Figure 8. C-PHY Ideal Single-Ended and Resulting Differential High-Speed Signals

........................ 39

Figure 9. GMSL2 Lock Time

.................................................................... 40

Figure 10. GMSL2 Video Latency

................................................................ 40

Figure 11. GMSL2 GPI-to-GPO Delay and Skew

.................................................... 40

Figure 12. GMSL1 Lock Time

................................................................... 40

Figure 13. GMSL1 Power-up Delay

................................................................41

Figure 14. GMSL1 Video Latency

.................................................................41

Figure 15. GMSL1 GPI-to-GPO Delay

..............................................................41

Figure 16. D-PHY HS Burst Data Transmission

..................................................... 42

Figure 17. D-PHY Data Clock Timing

............................................................. 42

Figure 18. D-PHY High-Speed Skew Calibration

.................................................... 43

Figure 19. D-PHY Switching Clock Lane From Active Transmission to Low-Power Mode

..................... 43

Figure 20. C-PHY HS Burst Data Transmission

..................................................... 44

Figure 21. I

C Timing Parameters ................................................................ 44

Figure 22. SPI Master Mode Timing Parameters

.................................................... 45

Figure 23. SPI Slave Mode Timing Parameters

..................................................... 45

Figure 24. Four Independent Sensors with Dedicated CSI-2 Interfaces

................................... 46

Figure 25. Four Independent Dual Sensors with Dedicated CSI-2 Interfaces

.............................. 47

Figure 26. Four Independent Sensors Aggregated to a Single CSI-2 Output

............................... 48

Figure 27. Four Independent Sensors Utilizing Partial Aggregation

...................................... 48

LIST OF FIGURES

TABLE OF CONTENTS

(

CONTINUED

)

www.maximintegrated.com

Maxim Integrated

│

MAX96712 Quad GMSL2 to CSI-2 Deserializer

with GMSL1 Compatibility

Figure 28. Four Independent Sensors Aggregated to a Single CSI-2 Stream and Replicated to 2 PHY Outputs ... 49

Figure 29. Four Independent Sensors with Mixed GMSL1/GMSL2 Links and Parallel/CSI-2 Video Ports

......... 49

Figure 30. Video Pipes and Routing

.............................................................. 52

Figure 31. MAX96712 Video Pipe Example with Partial FCFS Aggregation

................................ 52

Figure 32. Side-by-Side and Line-Interleaved Synchronous Aggregation Frame Formats

.................... 54

Figure 33. MAX96712 Video Pipe Example with Synchronous Aggregation

............................... 54

Figure 34. MAX96712 Video Pipe Example with FCFS Aggregation and Replication

........................ 55

Figure 35. I

C/UART Control Routing ............................................................. 57

Figure 36. I

C Write Packet Format............................................................... 70

Figure 37. I

C Read Packet Format ............................................................... 70

Figure 38. GMSL2 UART Protocol for Base Mode

................................................... 71

Figure 39. UART Data Format for Base Mode

...................................................... 72

Figure 40. UART Synchronization Frame

.......................................................... 72

Figure 41. UART Acknowledge Frame

............................................................. 72

Figure 42. UART Write Packet Format

............................................................ 73

Figure 43. UART Read Packet Format

............................................................ 73

Table 1. Recommended Operating Conditions

...................................................... 34

Table 2. External Component Requirements

........................................................ 34

Table 3. Control Channel Latency

................................................................ 59

Table 4. Typical GPIO Delays for Forward and Reverse Link Transmission

................................ 59

Table 5. Forward and Reverse Link Bandwidth Utilization

............................................. 61

Table 6. Feature Availability in GMSL1 Mode

....................................................... 63

Table 7. CFG0 Input Map

....................................................................... 64

Table 8. CFG1 Input Map

....................................................................... 65

Table 9. MFP Pin Function Map

.................................................................. 66

Table 10. MFP Pin Typical Output Rise and Fall Times

............................................... 67

Table 11. Suggested MFP Pin Speed Settings

...................................................... 67

Table 12. Recommended SPI Pin Programming

..................................................... 67

LIST OF TABLES

LIST OF FIGURES

(

CONTINUED

)

www.maximintegrated.com

Maxim Integrated

│

MAX96712 Quad GMSL2 to CSI-2 Deserializer

with GMSL1 Compatibility

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