List of figures AN4776
4/72 AN4776 Rev 3
List of figures
Figure 1. TIM1 timer-peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Relevant bloc diagram for the timer channel when configured as output . . . . . . . . . . . . . . . 8
Figure 3. Relevant bloc diagram for the timer channel when configured as input . . . . . . . . . . . . . . . 10
Figure 4. Input signal filtering (ETF [3:0]= 0100) : FSAMPLING = FDTS/2, N=6. . . . . . . . . . . . . . . . 12
Figure 5. Preload mechanism for timer channel register - disabled. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Preload mechanism for timer channel register - enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Synchronizing an STM32 timer by an external clock-signal . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Clock path for external clock-source modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Synchronization block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Timer counter increment (external clock mode 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Timer counter increment (external clock mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Synoptic of a frequency meters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Frequency meter architecture clocked by the internal HSI oscillator . . . . . . . . . . . . . . . . . 26
Figure 14. Frequency meter architecture clocked by the external clock-source mode 2 . . . . . . . . . . . 27
Figure 15. Timing diagram of input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. The PPM resulting of the internal source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. The PPM resulting of the external source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Project organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Architecture example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 21. Firmware source code organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22. Timing of clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 23. Timing of Break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 24. Timing of cycle-by-cycle regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25. Cycle-by-cycle regulation architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 26. Oscilloscope screen-shot for the obtained waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 27. Project organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 28. Configuration for a timer DMA-burst transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29. Synoptic schema of arbitrary waveform generation using DMA-burst . . . . . . . . . . . . . . . . 48
Figure 30. Arbitrary waveform generator application: targeted waveform . . . . . . . . . . . . . . . . . . . . . . 49
Figure 31. Waveform generation data pattern stored in microcontroller memory . . . . . . . . . . . . . . . . 51
Figure 32. Block diagram of arbitrary waveform generation example . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 33. Arbitrary signal generation on channel1 of TIM1 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 34. Periodic N-pulses generation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 35. Output waveform target of periodic N-pulses generation example . . . . . . . . . . . . . . . . . . . 59
Figure 36. Periodic N-pulses generation synoptic schema . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 37. Timing diagram of periodic N-pulses generation example . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 38. Synoptic schema of two complementary N pulses waveform generation example . . . . . . 64
Figure 39. Output of two N-pulses complimentary waveforms generation example . . . . . . . . . . . . . . 64
Figure 40. Timing diagram of complimentary N-pulses waveforms generation with similar final state 67
