用vhdl语言设计交通信号灯控制器

Debug for fit_fastio_pin_reassign program (iteration 1): I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 33 N/A 77 N/A N/A Clr N/A 21 N/A 65 N/A N/A Pre N/A 26 N/A 70 N/A N/A Ena N/A N/A 13 N/A N/A N/A Ald N/A 26 N/A 70 N/A N/A OE N/A N/A N/A 61 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 12 N/A 60 N/A N/A N/A A N/A N/A 13 65 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 25 32 N/A 32 N/A Clr : N/A 28 N/A N/A 35 N/A Pre : N/A 28 N/A N/A 35 N/A Ena : N/A N/A N/A N/A N/A N/A Ald : N/A 28 N/A N/A 35 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 16 N/A 2 N/A 2 19 Casc: 9 N/A N/A N/A N/A 12 Pin : N/A N/A N/A N/A N/A N/A A : 22 N/A 8 N/A 7 25 B : 20 N/A 6 N/A 7 23 C : 19 N/A 5 N/A N/A 22 D : 17 N/A 3 N/A N/A 20 I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 33 N/A 77 N/A N/A Clr N/A 21 N/A 65 N/A N/A Pre N/A 26 N/A 70 N/A N/A Ena N/A N/A 13 N/A N/A N/A Ald N/A 26 N/A 70 N/A N/A OE N/A N/A N/A 61 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 12 N/A 60 N/A N/A N/A A N/A N/A 13 65 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 25 32 N/A 32 N/A Clr : N/A 28 N/A N/A 35 N/A Pre : N/A 28 N/A N/A 35 N/A Ena : N/A N/A N/A N/A N/A N/A Ald : N/A 28 N/A N/A 35 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 16 N/A 2 N/A 2 19 Casc: 9 N/A N/A N/A N/A 12 Pin : N/A N/A N/A N/A N/A N/A A : 22 N/A 8 N/A 7 25 B : 20 N/A 6 N/A 7 23 C : 19 N/A 5 N/A N/A 22 D : 17 N/A 3 N/A N/A 20 Threshold are: for Tsu - 9.500000ns and for Tco - 23.100000ns Global Tsu=-1(-1.000000), Tco=-1(-1.000000) Input/output cells: A0 -> 191 : OUT A1 -> 192 : OUT A2 -> 193 : OUT A3 -> 195 : OUT B0 -> 179 : OUT B1 -> 187 : OUT B2 -> 189 : OUT B3 -> 190 : OUT CLK -> 79 : IN C0 -> 174 : OUT C1 -> 175 : OUT C2 -> 176 : OUT C3 -> 177 : OUT D0 -> 169 : OUT D1 -> 170 : OUT D2 -> 172 : OUT D3 -> 173 : OUT GREENA -> 90 : OUT GREENB -> 205 : OUT HOLD -> 65 : IN REDA -> 135 : OUT REDB -> 202 : OUT RESET -> 64 : IN YELLOWA -> 92 : OUT YELLOWB -> 198 : OUT Set clique dont_touch: Cell: A0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: A1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: A2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: A3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: B0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: B1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: B2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: B3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: CLK, rdfbits: d, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:121, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:125, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:129, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:133, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:137, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:4, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:6, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:8, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:10, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:12, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:14, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:16, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|~109~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:109, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|LPM_ADD_SUB:261|addcore:adder|pcarry4, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|LPM_ADD_SUB:261|addcore:adder|:125, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|LPM_ADD_SUB:314|addcore:adder|pcarry2, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|LPM_ADD_SUB:314|addcore:adder|pcarry4, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:10, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:12, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:14, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:16, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:18, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:20, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:22, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:24, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:26, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:28, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:30, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:32, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:34, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:36, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:38, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:40, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:42, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:44, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:148, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:163, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:188, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:203, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:401, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:407, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:419, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:422, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:431, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:434, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:447, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:448, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:458, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:597, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:607, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:796, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:808, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:817, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:826, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: C0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: C1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: C2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: C3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: D0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: D1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: D2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: D3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|LPM_ADD_SUB:295|addcore:adder|pcarry2, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|LPM_ADD_SUB:383|addcore:adder|:71, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:104, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:138, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:174, rdfbits: 50, fast_io bit: 0, p