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IXP1200 Prog Ref Manual
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Intel
®
IXP1200 Network
Processor Family
Microcode Programmer’s Reference Manual
December 2001
Part Number: 278304-010
ii Microcode Programmer’s Reference Manual
Intel
®
IXP1200 Network Processor Family
IInformation in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The IXP1200 Network Processor Family may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the
license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a
commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this
document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may
be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2001
Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries
*Other names and brands may be claimed as the property of others.
Revision History
Revision Date Revision Description
8/30/99 001 Beta 1 release.
10/6/99 002 Beta 2 release.
11/5/99 003 Beta 3 release.
3/2/00 004 Beta 4 release.
5/30/00 005 Version 1.0 release.
9/28/00 006 Version 1.1 release.
12/15/00 007 Version 1.2 release.
6/01/01 008
Version 1.3 SDK release. Retitled document to support the IXP1200, IXP1240,
and IXP1250.
8/15/01 009 Version 2.0 SDK release. Miscellaneous changes.
12/07/01 010 Version 2.01 SDK release. Miscellaneous changes.
Microcode Programmer’s Reference Manual iii
Intel
®
IXP1200 Network Processor Family
Contents
1 Introduction.......................................................................................................................17
1.1 About this Document ...........................................................................................17
1.2 Related Documentation.......................................................................................17
2 Assembler ........................................................................................................................19
2.1 Overview .............................................................................................................19
2.1.1 Data Terminology ...................................................................................19
2.2 Programming With Microengine Registers..........................................................20
2.2.1 General-Purpose Registers (GPRs).......................................................21
2.2.2 SDRAM Transfer Registers (SDRAM XFERs).......................................21
2.2.3 SRAM Transfer Registers (SRAM XFERs) ............................................21
2.2.4 Addressing Modes..................................................................................22
2.2.4.1 Context-Relative Addressing Mode...........................................22
2.2.4.2 Absolute Addressing Mode .......................................................22
2.2.5 Register Naming.....................................................................................22
2.2.6 GPR Register Banks ..............................................................................23
2.2.7 Local Registers.......................................................................................24
2.2.8 Register Allocation .................................................................................26
2.2.9 Address Operator ...................................................................................26
2.2.10 Array Notation ........................................................................................26
2.2.11 Flow Graph Analysis ..............................................................................27
2.3 New Register Allocation ......................................................................................27
2.3.1 Overview ................................................................................................27
2.3.2 Details ....................................................................................................28
2.3.3 Limitations ..............................................................................................30
2.3.4 Errors and Warnings ..............................................................................30
2.4 Microcode Elements............................................................................................32
2.4.1 Comments ..............................................................................................32
2.4.2 Directives................................................................................................33
2.4.3 Opcode Lines .........................................................................................33
2.5 Assembler Directives...........................................................................................33
2.5.1 Assembly Loops .....................................................................................34
2.5.1.1 For Loops ..................................................................................34
2.5.1.2 Repeat Loops ............................................................................35
2.5.1.3 While Loops...............................................................................35
2.5.2 Assembly Macros ...................................................................................35
2.5.3 Conditional Assembly.............................................................................36
2.5.4 Error Reporting.......................................................................................36
2.5.5 Export Function ......................................................................................37
2.5.6 File Inclusion ..........................................................................................38
2.5.7 Function Table........................................................................................38
2.5.8 Import Variables .....................................................................................38
2.5.9 Linker Directives.....................................................................................39
2.5.10 Local Regions.........................................................................................39
2.5.11 Manual Register Specification................................................................40
2.5.12 Operand Synonym .................................................................................41
iv Microcode Programmer’s Reference Manual
Intel
®
IXP1200 Network Processor Family
2.5.13 Structured Assembly .............................................................................. 41
2.5.13.1 Conditional Expressions...........................................................43
2.5.14 Subroutine Definition.............................................................................. 45
2.5.15 Token Replacement ...............................................................................45
2.5.16 Transfer Order........................................................................................47
2.5.17 Segment.................................................................................................47
2.5.18 Virtual Set...............................................................................................48
2.6 Preprocessor Details...........................................................................................48
2.6.1 Reserved Symbols .................................................................................48
2.6.2 Command Line Arguments ....................................................................48
2.6.3 Constant Expressions ............................................................................49
2.6.4 Preprocessor Operation .........................................................................51
2.6.5 Miscellaneous ........................................................................................52
2.6.6 Syntax for Argument and Token Lists .................................................... 52
2.6.7 Environment Variables ...........................................................................53
2.6.8 Predefined Symbols ...............................................................................53
2.6.9 Predefined Import Variables...................................................................53
2.7 Preprocessor Techniques ...................................................................................54
2.7.1 Branching into a Macro ..........................................................................54
2.7.2 Constructing Names from Numbers....................................................... 55
2.7.3 Writing Version Specific Code................................................................56
2.8 Distinguishing Preprocessor and Assembler Directives......................................57
3 Instruction Set ..................................................................................................................59
3.1 ALU .....................................................................................................................61
3.2 ALU_SHF ............................................................................................................ 63
3.3 BR .......................................................................................................................65
3.4 BR<0, BR=0, BR<=0, BR!=0, BR=COUT, BR>0 BR!=COUT, BR>=0................ 66
3.5 BR_BCLR, BR_BSET .........................................................................................67
3.6 BR=BYTE, BR!=BYTE ........................................................................................68
3.7 BR=CTX, BR!=CTX.............................................................................................69
3.8 BR_INP_STATE..................................................................................................70
3.9 BR_!SIGNAL.......................................................................................................71
3.10 CSR.....................................................................................................................72
3.11 CTX_ARB............................................................................................................74
3.12 DBL_SHF ............................................................................................................75
3.13 FAST_WR ...........................................................................................................76
3.14 FIND_BSET, FIND_BSET_WITH_MASK ...........................................................78
3.15 HASH1_48, HASH2_48, HASH3_48 ..................................................................81
3.16 HASH1_64, HASH2_64, HASH3_64 ..................................................................83
3.17 IMMED ................................................................................................................84
3.18 IMMED_B0, IMMED_B1, IMMED_B2, IMMED_B3.............................................85
3.19 IMMED_W0, IMMED_W1 ...................................................................................86
3.20 JUMP ..................................................................................................................87
3.21 LD_FIELD, LD_FIELD_W_CLR .......................................................................... 89
3.22 LOAD_ADDR ......................................................................................................90
3.23 LOAD_BSET_RESULT1, LOAD_BSET_RESULT2 ...........................................91
3.24 LOCAL_CSR_RD................................................................................................ 92
3.25 LOCAL_CSR_WR............................................................................................... 93
3.26 NOP ....................................................................................................................95
Microcode Programmer’s Reference Manual v
Intel
®
IXP1200 Network Processor Family
3.27 PCI_DMA ............................................................................................................96
3.28 R_FIFO_RD ........................................................................................................98
3.29 RTN...................................................................................................................103
3.30 SCRATCH .........................................................................................................104
3.31 SDRAM .............................................................................................................108
3.32 SDRAM_CRC....................................................................................................113
3.32.1 SDRAM_CRC [WRITE Command with TX_INITIATE or
RX_INITIATE].......................................................................................116
3.32.2 SDRAM_CRC [WRITE/READ Commands Without TX_INITIATE,
RX_INITIATE, or READ_RESIDUE Tokens]........................................118
3.32.3 SDRAM_CRC [R_FIFO_RD Command] ..............................................120
3.32.4 SDRAM_CRC [T_FIFO_WR Command]..............................................122
3.32.5 SDRAM_CRC [READ Command with READ_RESIDUE Token].........125
3.33 SRAM ................................................................................................................127
3.34 T_FIFO_WR......................................................................................................135
4 Register Descriptions .....................................................................................................139
4.1 Overview ...........................................................................................................139
4.1.1 Conventions .........................................................................................144
4.2 FBI Control and Status Registers......................................................................145
4.2.1 IREG.....................................................................................................145
4.2.2 SOP_SEQ1/SOP_SEQ2......................................................................147
4.2.2.1 SOP_SEQ1 .............................................................................147
4.2.2.2 SOP_SEQ2 .............................................................................147
4.2.3 ENQUEUE_SEQ1/ENQUEUE_SEQ2..................................................148
4.2.3.1 ENQUEUE_SEQ1 ...................................................................148
4.2.3.2 ENQUEUE_SEQ2 ...................................................................149
4.2.4 INTER_THD_SIG.................................................................................150
4.2.5 THREAD_DONE (THREAD_DONE_REG0/THREAD_DONE_REG1) 151
4.2.5.1 THREAD_DONE_REG0 .........................................................151
4.2.5.2 THREAD_DONE_REG1 .........................................................152
4.2.6 THREAD_DONE_INCR1/THREAD_DONE_INCR2 ............................153
4.2.7 RCV_RDY_CNT...................................................................................154
4.2.8 RCV_RDY_HI/RCV_RDY_LO..............................................................155
4.2.8.1 RCV_RDY_HI..........................................................................155
4.2.8.2 RCV_RDY_LO ........................................................................155
4.2.9 RCV_RDY_CTL ...................................................................................156
4.2.10 RCV_REQ ............................................................................................158
4.2.11 RCV_CNTL ..........................................................................................160
4.2.12 REC_FASTPORT_CTL........................................................................162
4.2.13 FP_READY_WAIT ...............................................................................163
4.2.14 RFIFO_ADDR ......................................................................................164
4.2.15 FLOWCTL_MASK ................................................................................165
4.2.16 RDYBUS_TEMPLATE_CTL.................................................................166
4.2.17 RDYBUS_TEMPLATE_PROG_3/RDYBUS_TEMPLATE_PROG_2/
RDYBUS_TEMPLATE_PROG_1.........................................................167
4.2.17.1RDYBUS_TEMPLATE_PROG_3............................................168
4.2.17.2RDYBUS_TEMPLATE_PROG_2............................................168
4.2.17.3RDYBUS_TEMPLATE_PROG_1............................................169
4.2.18 RDYBUS_SYNCH_COUNT_DEFAULT...............................................170
4.2.19 SELF_DESTRUCT...............................................................................171
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