Connectivity 4 of 99
ISP1362 Embedded Programming Guide Rev. 0.9
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7.1.1. Configuring the ISP1362............................................................................................................................................31
7.1.2. Setting the Host Controller to the Operational State and Enabling the Port..................................................................31
7.1.3. Some Backgrounds......................................................................................................................................................32
7.1.4. First Contact ..............................................................................................................................................................35
7.1.5. Reset and SetAddress..................................................................................................................................................36
7.2.
GET_CONTROL() FUNCTION..........................................................................................................................................38
7.2.1. Getting Descriptors .....................................................................................................................................................42
7.3.
SET_CONFIG FUNCTION .................................................................................................................................................42
8. ADVANCED FEATURE 1: MULTI-FRAME BUFFERING OF THE ISO TRANSFER ........................44
8.1. C
ONFIGURATION OF THE ISO BUFFER .......................................................................................................................45
8.2. ISO PTD F
ORMAT ..........................................................................................................................................................45
8.3. M
ULTI-FRAME BUFFERING CONTROL REGISTERS.....................................................................................................45
8.3.1. Multi-Frame Buffering Mechanism..............................................................................................................................45
8.4. T
RAFFIC, HOST CONTROLLER AND CPU ACTIVITIES ...............................................................................................46
9. ADVANCED FEATURE 2: PAIRED-PTD FOR THE BULK TRANSFER..............................................47
9.1. C
ONFIGURATION OF THE ATL BUFFER ......................................................................................................................47
9.2. PTD F
ORMAT OF PAIRED PTD ....................................................................................................................................47
9.3. R
EGISTERS FOR PAIRED-PTD MECHANISM CONTROL .............................................................................................48
9.4. D
ONE, SKIP, LAST...........................................................................................................................................................48
9.5. P
AIRED-PTD BUFFERING MECHANISM ......................................................................................................................48
10. ADVANCED FEATURE 3: AUTOMATIC POLLING FOR THE INTERRUPT ENDPOINT .........50
10.1. C
ONFIGURING THE INTL BUFFER ..........................................................................................................................50
10.2. I
NTERRUPT PTD FORMAT.........................................................................................................................................50
10.3. R
EGISTERS FOR THE INTERRUPT AUTOMATIC POLLING CONTROL ...................................................................50
10.4. D
ONE, SKIP, LAST ......................................................................................................................................................51
10.5. I
NTERRUPT AUTOMATIC POLLING CONTROL ........................................................................................................51
11. ON-THE-GO—HNP AND SRP ...............................................................................................................52
11.1. I
NTRODUCTION...........................................................................................................................................................52
11.2. OTG R
EGISTERS.........................................................................................................................................................52
11.2.1. Register Sets................................................................................................................................................................52
11.2.2. Register Access............................................................................................................................................................52
11.3. P
ROGRAMMING SRP...................................................................................................................................................52
11.3.1. B-Device Initiating SRP .............................................................................................................................................52
11.3.2. A-Device Detecting SRP.............................................................................................................................................54
11.4. P
ROGRAMMING HNP STATE MACHINE..................................................................................................................54
11.4.1. HNP State Machine (OTG_FSM)...........................................................................................................................54
11.4.2. Procedures for Handling HNP....................................................................................................................................54
11.4.3. OTG Interrupt...........................................................................................................................................................55
11.4.4. Using OtgTimer and OtgAltTimer .............................................................................................................................57
11.4.5. Using Auto Connect ...................................................................................................................................................57
11.4.6. Using Auto Bus Reset ................................................................................................................................................57
11.4.7. Using OtgInterrupt to Wake-up the Chip....................................................................................................................58
11.5. OTG HNP S
TATE MACHINE PSEUDO CODE ........................................................................................................58
11.5.1. Dual-Role A-Device State Machine ............................................................................................................................58
11.5.2. Dual-Role B-Device State Machine .............................................................................................................................60
11.6. P
OWER SAVING AND CHIP WAKE-UP ......................................................................................................................62
11.6.1. Suspending the Host Controller ...................................................................................................................................62
11.6.2. Suspending the Device Controller .................................................................................................................................62
11.6.3. Resuming the Host Controller......................................................................................................................................63
11.6.4. Resuming the Device Controller ...................................................................................................................................63
11.6.5. ISP1362 in Minimum Power Current State and Wake-Up Method ...........................................................................63