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Vivado Design Suite

Tutorial

Partial Reconfiguration

UG947 (v2018.1) April 27, 2018

UG947 (v2018.2) July 13, 2018

This tutorial was validated with 2018.1. Minor procedural differences might be required when

using later releases.

Partial Reconfiguration www.xilinx.com 3

UG947 (v2018.1) April 27, 2018

Table of Contents

Revision History ........................................................................................................................................................... 2

Introduction .................................................................................................................................................................... 6

Overview ........................................................................................................................................................................ 6

Hardware and Software Requirements .............................................................................................................. 7

Tutorial Design Description .................................................................................................................................... 7

Lab 1: 7 Series Basic Partial Reconfiguration Flow ........................................................................................... 10

Overview ...................................................................................................................................................................... 10

Step 1: Extracting the Tutorial Design Files .................................................................................................... 10

Step 2: Examining the Scripts ............................................................................................................................... 10

Step 3: Synthesizing the Design .......................................................................................................................... 12

Step 4: Assembling and Implementing the Design ..................................................................................... 12

Step 5: Building the Design Floorplan .............................................................................................................. 14

Step 6: Implementing the First Configuration ............................................................................................... 20

Step 7: Implementing the Second Configuration ......................................................................................... 25

Step 8: Examining the Results with Highlighting Scripts ........................................................................... 27

Step 9: Generating Bitstreams ............................................................................................................................. 28

Step 10: Partially Reconfiguring the FPGA ...................................................................................................... 30

Conclusion ................................................................................................................................................................... 31

Lab 2: UltraScale Basic Partial Reconfiguration Flow ....................................................................................... 32

Overview ...................................................................................................................................................................... 32

Step 1: Extracting the Tutorial Design Files .................................................................................................... 32

Step 2: Examining the Scripts ............................................................................................................................... 32

Step 3: Synthesizing the Design .......................................................................................................................... 34

Step 4: Assembling and Implementing the Design ..................................................................................... 34

Step 5: Building the Design Floorplan .............................................................................................................. 36

Step 6: Implementing the First Configuration ............................................................................................... 39

Step 7: Implementing the Second Configuration ......................................................................................... 44

Step 8: Examining the Results with Highlighting Scripts ........................................................................... 46

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UG947 (v2018.2) July 13, 2018

Table of Contents

Partial Reconfiguration www.xilinx.com 4

UG947 (v2018.1) April 27, 2018

Step 9: Generating the Bitstreams ..................................................................................................................... 48

Step 10: Partially Reconfiguring the FPGA ...................................................................................................... 51

Conclusion ................................................................................................................................................................... 52

Lab 3: Partial Reconfiguration Project Flow ........................................................................................................ 53

Overview ...................................................................................................................................................................... 53

Step 1: Extracting the Tutorial Design Files .................................................................................................... 53

Step 2: Loading Initial Design Sources ............................................................................................................. 53

Step 3: Completing the Design with the Partial Reconfiguration Wizard ........................................... 57

Step 4: Synthesizing and Implementing the Current Design ................................................................... 61

Step 5: Adding an Additional Reconfigurable Module and Corresponding Configuration ......... 65

Step 6: Creating and Implementing a Greybox Module ............................................................................ 68

Step 6: Modifying a Design Source or Options ............................................................................................. 70

Conclusion ................................................................................................................................................................... 71

Lab 4: Vivado Debug and the PR Project Flow .................................................................................................. 72

Overview ...................................................................................................................................................................... 72

Step 1: Loading Initial Design Sources ............................................................................................................. 72

Step 2: Setting Up the Design for Partial Reconfiguration ....................................................................... 75

Step 3: Using the Partial Reconfiguration Wizard to Complete the Rest of the Design ............... 78

Step 4: Adding IP within the Reconfigurable Module ................................................................................ 81

Step 5: Synthesizing the Design and Creating a Floorplan ...................................................................... 83

Step 6: Running the PR Configuration Analysis Report ............................................................................. 87

Step 7: Implementing the Design ....................................................................................................................... 88

Step 8: Adding an Additional Reconfigurable Module and Corresponding Configuration ......... 92

Step 9: Generating Bitstreams ............................................................................................................................. 96

Step 10: Connecting to the Board and Programing the FPGA ................................................................ 96

Conclusion ................................................................................................................................................................ 103

Lab 5: Partial Reconfiguration Controller IP for 7 Series Devices ............................................................ 104

Step 1: Extracting the Tutorial Design Files ................................................................................................. 104

Step 2: Customizing the Partial Reconfiguration Controller IP ............................................................ 104

Step 3: Compiling the Design ........................................................................................................................... 111

Step 4: Setting up the Board ............................................................................................................................. 112

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UG947 (v2018.2) July 13, 2018

Table of Contents

Partial Reconfiguration www.xilinx.com 5

UG947 (v2018.1) April 27, 2018

Step 5: Operating the Sample Design ........................................................................................................... 113

Step 6: Querying the PRC in the FPGA .......................................................................................................... 115

Step 7: Modifying the PRC in the FPGA ........................................................................................................ 117

Conclusion ................................................................................................................................................................ 119

Lab 6: Partial Reconfiguration Controller IP for UltraScale Devices ........................................................ 120

Step 1: Extracting the Tutorial Design Files ................................................................................................. 120

Step 2: Customizing the Partial Reconfiguration Controller IP ............................................................ 120

Step 3: Compiling the Design ........................................................................................................................... 127

Step 4: Setting up the Board ............................................................................................................................. 128

Step 5: Operating the Sample Design ........................................................................................................... 128

Step 6: Querying the PRC in the FPGA .......................................................................................................... 129

Step 7: Modifying the PRC in the FPGA ........................................................................................................ 131

Conclusion ................................................................................................................................................................ 133

Legal Notices ............................................................................................................................................................... 134

Please Read: Important Legal Notices ........................................................................................................... 134

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UG947 (v2018.2) July 13, 2018