CUPL-to-PEELÔ (v2.0)
¾¾¾¾¾¾¾¾¾¾
PEEL-Array Device Fitters
for CUPL 4.5 or greater
Trademarks
PEELÔ, APEELÔ and PLACEÔ are trademarks of ICT, Inc.
CUPLÔ is a trademark of Logical Devices Inc.
ABELÔ and OPEN-ABELÔ are trademarks of Data I/O Corporation
CUPL-to-PEELÔ User Manual
Copyright 1994, ICT, Inc.
ICT, Inc.
2123 Ringwood Ave.
San Jose CA, 95131
Phone: (408) 434-0678
Fax: (408) 432-08
April 94 1 ICT Inc.
Table of Contents
Page
1.0 CUPL-to-PEEL Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 About CUPL-to-PEEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 About this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 PEEL Array Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Upgrades to CUPL-to-PEEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.0 CUPL-to-PEEL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Using CUPL with PEEL Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Executing CUPL-to-PEEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.0 CUPL Design Rules for PEEL Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 PEEL Array design rules overview . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 The "Property" statement . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 8
3.3 Pin and Node Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Dot Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.0 Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Appendix A. Source File Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
April 94 2 ICT Inc.
1.0 Introduction
1.1 About CUPL-to-PEEL
CUPL-to-PEEL (v2.0) Device Fitters allow designers to create programming files for ICT's
PEEL Array family (PA7024, PA7128, PA7140) using CUPL 4.5 (or greater) high-level
design language from Logical Devices. The CUPL development methodology is fully
maintained through design entry, compilation and functional simulation. The fitter operates
on "Berkeley Espresso" PLA files, that are produced by the CUPL compiler, and creates
PEEL Array JEDEC programming files.
CUPL-to-PEEL Device Fitters provide true device independent design entry, therefore, it is
not necessary to specify pin numbers, node numbers, global clock, reset or preset nodes. The
fitters automatically optimizes the placement of signals on logic cells and I/Os for the best fit.
This feature eases the conversion from other PLD designs. A detailed description of the
configuration selected by the fitter is stored in a ".log" file.
The fitters also allow use of the PLACE software by optionally creating a ".psf" extension file
which allows for architectural viewing of the design in PLACE software. This makes it
possible to simulate test vectors stored in the JEDEC file while using the PLACE software.
The CUPL-to-PEEL fitters operate on PC compatibles with DOS 3.0 or greater.
1.2 About this Manual
This manual includes operation and reference information for using ICT's CUPL-to-PEEL
software (version 2.0). It is meant to be used in conjunction with Logical Devices' CUPL
PLD/FPGA Language Compiler. We recommend you first become familiar with CUPL
using the CUPL manual before proceeding with CUPL-to-PEEL.
April 94 3 ICT Inc.
1.3 PEEL-ArrayÔ Architecture
Programmable Electrically Erasable Logic (PEELÔ) Arrays are a family of Complex
Programmable Logic Devices (CPLDs) based on ICT's CMOS EEPROM technology. PEEL
Arrays free designers from the limitations of ordinary PLDs by providing the architectural
flexibility and the speed needed for today's programmable logic designs.
The initial PEEL Array family consists of three parts: the PA7024, PA7128 and PA7140, in
packages ranging from 24 to 44 pins in plastic DIP, PLCC, and SOIC formats. ICT's CMOS
EE technology allows reprogramability and high-speed performance. Wide-gate delays as fast
as 9ns for internal (buried) and 15ns external (pin to pin) are possible with PEEL Arrays.
Clock frequencies can be as fast as 76.9MHz for sequential functions.
The PEEL Array architecture is based on a versatile multi-level logic array architecture rich
in input latches, buried registers and sum-of-product logic functions. The basic logic array
structure is similar to that of a PLA (programmable AND, programmable OR) allowing true
product term sharing.
PEEL Arrays offer the most flexible logic and I/O cells of any CPLD available today. The
unique PEEL Array logic cell incorporates multiple outputs allowing registers and
combinational logic to be buried without limiting the use of I/O pins as with other CPLDs.
Logic cell registers are user-configurable to be true D, T and JK registers with independent or
global clocks, resets, presets, clock polarity and other special features. Additionally, all
registers and output enables allow full sum-of-products control.
PEEL Arrays are ideal for implementing a wide variety of general purpose combinational,
synchronous and asynchronous logic applications, including: buried counters, complex state-
machines, comparitors, decoders, encoders, adders, address/data demux and other wide-gate
logic. Because PEEL Arrays allow for multi-level buried logic, designs normally requiring
multiple PLDs and/or random logic can be efficiently integrated. For further information on
PEEL Arrays please refer to the ICT Data Book.
1.4 Upgrades to CUPL-to-PEEL
Upgrades to CUPL-to-PEEL can be download from the ICT or the Logical Devices bulletin
boards.
ICT Inc. BBS:
Modem number: (408) 434-0130
Baud rate: 9600 or lower
Parity: None
Date bit: 8
Stop bit: 1
April 94 4 ICT Inc.
